25 Ques On Vlsi Digital 1e2346
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VLSI Interview Questions and Answers :1. Why does the present VLSI circuits use MOSFETs instead of BJTs?
Compared to BJTs, MOSFETs can be made very small as they occupy very small
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silicon area on IC chip and are relatively simple in of manufacturing.
Moreover digital and memory ICs can be implemented with circuits that use only MOSFETs i.e. no resistors, diodes, etc.
2. What are the various regions of operation of MOSFET? How are those regions used?
MOSFET has three regions of operation: the cut-off region, the triode region, and the saturation region.
The cut-off region and the triode region are used to operate as switch. The saturation region is used to operate as amplifier. 3. What is threshold voltage? The value of voltage between Gate and Source i.e. VGS at which a sufficient number of mobile electrons accumulate in the channel region to form a
conducting channel is called threshold voltage (Vt is positive for NMOS and negative for PMOS).
VLSI Interview Questions and Answers
4. What does it mean “the channel is pinched off”? For a MOSFET when VGS is greater than Vt, a channel is induced. As we
increase VDS current starts flowing from Drain to Source (triode region). When we further increase VDS, till the voltage between gate and channel at the drain end to become Vt, i.e. VGS – VDS = Vt, the channel depth at Drain end
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decreases almost to zero, and the channel is said to be pinched off. This is where a MOSFET enters saturation region.
5. Explain the three regions of operation of a MOSFET. Cut-off region: When VGS < Vt, no channel is induced and the MOSFET will be in cut-off region. No current flows.
Triode region: When VGS ≥ Vt, a channel will be induced and current starts
flowing if VDS > 0. MOSFET will be in triode region as long as VDS < VGS – Vt. Saturation region: When VGS ≥ Vt, and VDS ≥ VGS – Vt, the channel will be in saturation mode, where the current value saturates. There will be little or no effect on MOSFET when VDS is further increased. 6. What is channel-length modulation? In practice, when VDS is further increased beyond saturation point, it does has some effect on the characteristics of the MOSFET. When VDS is increased the channel pinch-off point starts moving away from the Drain and towards the Source. Due to which the effective channel length decreases, and this phenomenon is called as Channel Length Modulation. 7. Explain depletion region. When a positive voltage is applied across Gate, it causes the free holes (positive charge) to be repelled from the region of substrate under the Gate (the channel region). When these holes are pushed down the substrate they leave behind a carrier-depletion region.
8. What is body effect? Usually, in an integrated circuit there will be several MOSFETs and in order to maintain cut-off condition for all MOSFETs the body substrate is connected to
the most negative power supply (in case of PMOS most positive power supply). 04-10-2016 16:06
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Which causes a reverse bias voltage between source and body that effects the
transistor operation, by widening the depletion region. The widened depletion region will result in the reduction of channel depth. To restore the channel
depth to its normal depth the VGS has to be increased. This is effectively seen
as change in the threshold voltage – Vt. This effect, which is caused by applying some voltage to body is known as body effect.
9. Give various factors on which threshold voltage depends. As discussed in the above question, the Vt depends on the voltage connected to the Body terminal. It also depends on the temperature, the magnitude of Vt decreases by about 2mV for every 1oC rise in temperature.
10. Give the Cross-sectional diagram of the CMOS.
11. What is the fundamental difference between a MOSFET and BJT ?
In MOSFET, current flow is either due to electrons(n-channel MOS) or due to holes(p-channel MOS) – In BJT, we see current due to both the carriers..
electrons and holes. BJT is a current controlled device and MOSFET is a voltage controlled device.
12. Why are most interrupts active low? If you consider the transistor level of a module, active low means the capacitor
in the output terminal gets charged or discharged based on low to high and high to low transition, respectively. when it goes from high to low it depends on the pull down resistor that pulls it down and it is relatively easy for the output
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capacitance to discharge rather than charging. Hence designers prefer active low interrupt signals.
13. Which is better: synchronous reset or asynchronous reset signal?
Click here to learn more about synchronous reset and asynchronous reset. Synchronous reset logic will synthesize to smaller flip-flops, particularly if the reset is gated with the logic generating the d-input. But in such a case, the
combinational logic gate count grows, so the overall gate count savings may not be that significant. The clock works as a filter for small reset glitches; however, if these glitches occur near the active clock edge, the Flip-flop could go
metastable. In some designs, the reset must be generated by a set of internal conditions. A synchronous reset is recommended for these types of designs because it will filter the logic equation glitches between clock.
Problem with synchronous resets is that the synthesis tool cannot easily
distinguish the reset signal from any other data signal. Synchronous resets may need a pulse stretcher to guarantee a reset pulse width wide enough to ensure reset is present during an active edge of the clock, if you have a gated clock to save power, the clock may be disabled coincident with the assertion of reset. Only an asynchronous reset will work in this situation, as the reset might be
removed prior to the resumption of the clock. Designs that are pushing the limit for data path timing, can not afford to have added gates and additional net delays in the data path due to logic inserted to handle synchronous resets.
Asynchronous reset: The major problem with asynchronous resets is the reset
release, also called reset removal. Using an asynchronous reset, the designer is guaranteed not to have the reset added to the data path. Another advantage
favoring asynchronous resets is that the circuit can be reset with or without a clock present. Ensure that the release of the reset can occur within one clock
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period else if the release of the reset occurred on or near a clock edge then flip-flops may go into metastable state.
14. Why is the number of gate inputs to CMOS gates (e.g. NAND or NOR gates)usually limited to four?
To limit the height of the stack. The higher the stack the slower the gate will be. In NAND and NOR gates the number of gates present in the stack is usually same as the number of inputs plus one. So inputs are limited to four.
15.On what factors does the resistance of metal depend on? R = (p.l)/A Where
R = Resistance of the metal. p = Resistivity of the metal.
A = is the cross sectional area. l = length of the metal.
With increase in length or decrease in cross sectional area resistance of the
metal wire increases. Resistivity(p) is the material property which depends on temperature. In general, resistivity of metals increases with temperature. This sections contains interview questions related to LOW POWER VLSI DESIGN.
16.What are the important aspects of VLSI optimization? Power, Area, and Speed. 17.What are the sources of power dissipation? + Dynamic power consumption, due to logic transitions causing logic gates to charge/discharge load capacitance.
+ Short-circuit current, this occurs when p-tree and n-tree shorted (for a while) 04-10-2016 16:06
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during logic transition.
+ Leakage current, this is a very important source of power dissipation in nano
technology, it increases with decrease in lambda value. It is caused due to diode leakages around transistors and n-wells.
18.What is the need for power reduction? Low power increases noise immunity, increases batter life, decreases cooling and packaging costs.
19.Give some low power design techniques. Voltage scaling, transistor resizing, pipelining and parallelism, power management modes like standby modes, etc.
20.Give a disadvantage of voltage scaling technique for power reduction.
When voltage is scaled, designers tend to decrease threshold voltage to
maintain good noise margins. But decreasing threshold voltages increases leakage currents exponentially.
21.Give an expression for switching power dissipation. Pswitching = (1/2)CVdd2f Where
Pswitching = Switching power. C = Load capacitance.
Vdd = Supply voltage.
f = Operating frequency. 22.Will glitches in a logic circuit cause power wastage? Yes, because they cause unexpected transitions in logic gates. 23.What is the major source of power wastage in SRAM? 04-10-2016 16:06
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To read/write a word data, activates a word line for a row which causes all the columns in the row to be active even though we need only a word data. This consumes a lot power.
24.What is the major problem associated with caches w.r.t low power design? Give techniques to overcome it.
Cache is a very important part of the integrated chips, they occupy most of the space and hence contain lot of transistors. More transistors means more
leakage current. That is the major problem associated with caches w.r.t. low
power design. The following techniques are used to overcome it: Vdd-Gating, Cache decay, Drowsy caches, etc.
25.Does software play any role in low power design? Yes, one can redesign a software to reduce power consumptions. For example modify the process algorithm which uses less number of computations.
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Below are the list of top VLSI interview questions and answers for freshers beginners and experienced pdf free .
VLSI Interview Questions and Answers :1. Why does the present VLSI circuits use MOSFETs instead of BJTs?
Compared to BJTs, MOSFETs can be made very small as they occupy very small
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silicon area on IC chip and are relatively simple in of manufacturing.
Moreover digital and memory ICs can be implemented with circuits that use only MOSFETs i.e. no resistors, diodes, etc.
2. What are the various regions of operation of MOSFET? How are those regions used?
MOSFET has three regions of operation: the cut-off region, the triode region, and the saturation region.
The cut-off region and the triode region are used to operate as switch. The saturation region is used to operate as amplifier. 3. What is threshold voltage? The value of voltage between Gate and Source i.e. VGS at which a sufficient number of mobile electrons accumulate in the channel region to form a
conducting channel is called threshold voltage (Vt is positive for NMOS and negative for PMOS).
VLSI Interview Questions and Answers
4. What does it mean “the channel is pinched off”? For a MOSFET when VGS is greater than Vt, a channel is induced. As we
increase VDS current starts flowing from Drain to Source (triode region). When we further increase VDS, till the voltage between gate and channel at the drain end to become Vt, i.e. VGS – VDS = Vt, the channel depth at Drain end
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decreases almost to zero, and the channel is said to be pinched off. This is where a MOSFET enters saturation region.
5. Explain the three regions of operation of a MOSFET. Cut-off region: When VGS < Vt, no channel is induced and the MOSFET will be in cut-off region. No current flows.
Triode region: When VGS ≥ Vt, a channel will be induced and current starts
flowing if VDS > 0. MOSFET will be in triode region as long as VDS < VGS – Vt. Saturation region: When VGS ≥ Vt, and VDS ≥ VGS – Vt, the channel will be in saturation mode, where the current value saturates. There will be little or no effect on MOSFET when VDS is further increased. 6. What is channel-length modulation? In practice, when VDS is further increased beyond saturation point, it does has some effect on the characteristics of the MOSFET. When VDS is increased the channel pinch-off point starts moving away from the Drain and towards the Source. Due to which the effective channel length decreases, and this phenomenon is called as Channel Length Modulation. 7. Explain depletion region. When a positive voltage is applied across Gate, it causes the free holes (positive charge) to be repelled from the region of substrate under the Gate (the channel region). When these holes are pushed down the substrate they leave behind a carrier-depletion region.
8. What is body effect? Usually, in an integrated circuit there will be several MOSFETs and in order to maintain cut-off condition for all MOSFETs the body substrate is connected to
the most negative power supply (in case of PMOS most positive power supply). 04-10-2016 16:06
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Which causes a reverse bias voltage between source and body that effects the
transistor operation, by widening the depletion region. The widened depletion region will result in the reduction of channel depth. To restore the channel
depth to its normal depth the VGS has to be increased. This is effectively seen
as change in the threshold voltage – Vt. This effect, which is caused by applying some voltage to body is known as body effect.
9. Give various factors on which threshold voltage depends. As discussed in the above question, the Vt depends on the voltage connected to the Body terminal. It also depends on the temperature, the magnitude of Vt decreases by about 2mV for every 1oC rise in temperature.
10. Give the Cross-sectional diagram of the CMOS.
11. What is the fundamental difference between a MOSFET and BJT ?
In MOSFET, current flow is either due to electrons(n-channel MOS) or due to holes(p-channel MOS) – In BJT, we see current due to both the carriers..
electrons and holes. BJT is a current controlled device and MOSFET is a voltage controlled device.
12. Why are most interrupts active low? If you consider the transistor level of a module, active low means the capacitor
in the output terminal gets charged or discharged based on low to high and high to low transition, respectively. when it goes from high to low it depends on the pull down resistor that pulls it down and it is relatively easy for the output
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capacitance to discharge rather than charging. Hence designers prefer active low interrupt signals.
13. Which is better: synchronous reset or asynchronous reset signal?
Click here to learn more about synchronous reset and asynchronous reset. Synchronous reset logic will synthesize to smaller flip-flops, particularly if the reset is gated with the logic generating the d-input. But in such a case, the
combinational logic gate count grows, so the overall gate count savings may not be that significant. The clock works as a filter for small reset glitches; however, if these glitches occur near the active clock edge, the Flip-flop could go
metastable. In some designs, the reset must be generated by a set of internal conditions. A synchronous reset is recommended for these types of designs because it will filter the logic equation glitches between clock.
Problem with synchronous resets is that the synthesis tool cannot easily
distinguish the reset signal from any other data signal. Synchronous resets may need a pulse stretcher to guarantee a reset pulse width wide enough to ensure reset is present during an active edge of the clock, if you have a gated clock to save power, the clock may be disabled coincident with the assertion of reset. Only an asynchronous reset will work in this situation, as the reset might be
removed prior to the resumption of the clock. Designs that are pushing the limit for data path timing, can not afford to have added gates and additional net delays in the data path due to logic inserted to handle synchronous resets.
Asynchronous reset: The major problem with asynchronous resets is the reset
release, also called reset removal. Using an asynchronous reset, the designer is guaranteed not to have the reset added to the data path. Another advantage
favoring asynchronous resets is that the circuit can be reset with or without a clock present. Ensure that the release of the reset can occur within one clock
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period else if the release of the reset occurred on or near a clock edge then flip-flops may go into metastable state.
14. Why is the number of gate inputs to CMOS gates (e.g. NAND or NOR gates)usually limited to four?
To limit the height of the stack. The higher the stack the slower the gate will be. In NAND and NOR gates the number of gates present in the stack is usually same as the number of inputs plus one. So inputs are limited to four.
15.On what factors does the resistance of metal depend on? R = (p.l)/A Where
R = Resistance of the metal. p = Resistivity of the metal.
A = is the cross sectional area. l = length of the metal.
With increase in length or decrease in cross sectional area resistance of the
metal wire increases. Resistivity(p) is the material property which depends on temperature. In general, resistivity of metals increases with temperature. This sections contains interview questions related to LOW POWER VLSI DESIGN.
16.What are the important aspects of VLSI optimization? Power, Area, and Speed. 17.What are the sources of power dissipation? + Dynamic power consumption, due to logic transitions causing logic gates to charge/discharge load capacitance.
+ Short-circuit current, this occurs when p-tree and n-tree shorted (for a while) 04-10-2016 16:06
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during logic transition.
+ Leakage current, this is a very important source of power dissipation in nano
technology, it increases with decrease in lambda value. It is caused due to diode leakages around transistors and n-wells.
18.What is the need for power reduction? Low power increases noise immunity, increases batter life, decreases cooling and packaging costs.
19.Give some low power design techniques. Voltage scaling, transistor resizing, pipelining and parallelism, power management modes like standby modes, etc.
20.Give a disadvantage of voltage scaling technique for power reduction.
When voltage is scaled, designers tend to decrease threshold voltage to
maintain good noise margins. But decreasing threshold voltages increases leakage currents exponentially.
21.Give an expression for switching power dissipation. Pswitching = (1/2)CVdd2f Where
Pswitching = Switching power. C = Load capacitance.
Vdd = Supply voltage.
f = Operating frequency. 22.Will glitches in a logic circuit cause power wastage? Yes, because they cause unexpected transitions in logic gates. 23.What is the major source of power wastage in SRAM? 04-10-2016 16:06
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To read/write a word data, activates a word line for a row which causes all the columns in the row to be active even though we need only a word data. This consumes a lot power.
24.What is the major problem associated with caches w.r.t low power design? Give techniques to overcome it.
Cache is a very important part of the integrated chips, they occupy most of the space and hence contain lot of transistors. More transistors means more
leakage current. That is the major problem associated with caches w.r.t. low
power design. The following techniques are used to overcome it: Vdd-Gating, Cache decay, Drowsy caches, etc.
25.Does software play any role in low power design? Yes, one can redesign a software to reduce power consumptions. For example modify the process algorithm which uses less number of computations.
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