Datasheet Of Texas Instruments Ic Series Cd40xx 55zg

Data sheet acquired from Harris Semiconductor SCHS015

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Copyright  1999, Texas Instruments Incorporated

This datasheet has been ed from: www.DatasheetCatalog.com Datasheets for electronic components.









CD4007M/CD4007C Dual Complementary Pair Plus Inverter General Description

Features

The CD4007M/CD4007C consists of three complementary pairs of N- and P-channel enhancement mode MOS transistors suitable for series/shunt applications. All inputs are protected from static discharge by diode clamps to VDD and VSS. For proper operation the voltages at all pins must be constrained to be between VSS b 0.3V and VDD a 0.3V at all times.

Y Y

Wide supply voltage range High noise immunity

3.0V to 15V 0.45 VCC (typ.)

Connection Diagram Dual-In-Line Package

TL/F/5943 – 1

Top View Note: All P-channel substrates are connected to VDD and all N-channel substrates are connected to VSS.

Order Number CD4007

C1995 National Semiconductor Corporation

TL/F/5943

RRD-B30M105/Printed in U. S. A.

CD4007M/CD4007C Dual Complementary Pair Plus Inverter

February 1988

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please the National Semiconductor Sales Office/Distributors for availability and specifications. Voltage at Any Pin

Storage Temperature Range Power Dissipation (PD) Dual-In-Line Small Outline Operating VDD Range

VSS b0.3V to VDD a 0.3V

Operating Temperature Range CD4007M CD4007C

b 55§ C to a 125§ C b 40§ C to a 85§ C

b 65§ C to a 150§ C

700 mW 500 mW VSS a 3.0V to VSS a 15V

Lead Temperature (Soldering, 10 seconds)

260§ C

DC Electrical Characteristics CD4007M Limits Symbol

Parameter

b 55§ C

Conditions Min

a 25§ C

a 125§ C

Typ Max Min

Typ Max

Min

Units

Typ Max

IL

Quiescent Device Current

VDD e 5.0V VDD e 10V

0.05 0.1

0.001 0.05 0.001 0.1

3.0 6.0

mA mA

PD

Quiescent Device VDD e 5.0V Dissipation Package VDD e 10V

0.25 1.0

0.005 0.25 0.001 1.0

15 60

mW mW

VOL

Output Voltage Low Level


0.05 0.05

0.05 0.05

V V

VOH

Output Voltage High Level


VNL

Noise Immunity (All Inputs)

VNH


VDD e 5.0V, VO e 3.6V VDD e 10V, VO e 7.2V VDD e 50V, VO e 0.95V VDD e 10V, VO e 2.9V

IDN

Output Drive Current VDD e 5.0V, VO e 0.4V, VI e VDD 0.75 N-Channel VDD e 10V, VO e 0.5V, VI e VDD 1.6 Output Drive Current VDD e 5.0V, VO e 2.5V, VI e VSS b1.75 P-Channel VDD e 10V, VO e 9.5V, VI e VSS b1.35

IDP II

4.95 9.95

0 0 4.95 9.95

1.5 3.0 3.6 7.1

0.05 0.05

5.0 10 2.25 4.5

4.95 9.95

V V

1.5 3.0

1.4 2.9

V V

3.5 7.0

2.25 4.5

3.5 7.0

V V

0.6 1.3

1.0 2.5

0.4 0.95

mA mA

b 1.0 b 0.75

mA mA

b 1.4 b 4.0 b 1.1 b 2.5

Input Current

10

pA

DC Electrical Characteristics CD4007C Limits Symbol

Parameter

b 40§ C

Conditions Min

a 25§ C

Typ Max

Min

a 85§ C

Typ Max

Min

Units

Typ Max

IL



0.5 1.0

0.005 0.05 0.005 1.0

15 30

mA mA

PD

Quiescent Device VDD e 5.0V Dissipation Package VDD e 10V

2.5 10

0.025 2.5 0.05 10

75 300

mW mW

VOL



0.05 0.05

0.05 0.05

V V

VOH



VNL

Noise Immunity (All inputs)

VNH


VDD e 5.0V, VO e 3.6V VDD e 10V, VO e 7.2V VDD e 5.0V, VO e 0.95V VDD e 10V, VO e 2.9V

IDN

Output Drive Current VDD e 5.0V, VO e 0.4V, VI e VDD 0.35 N-Channel VDD e 10V, VO e 0.5V, VI e VDD 1.2 Output Drive Current VDD e 5.0V, VO e 2.5V, VI e VSS b1.3 P-Channel VDD e 10V, VO e 9.5V, VI e VSS b0.65

IDP II

4.95 9.95

0 0 4.95 9.95

1.5 3.0 3.6 7.1

Input Current

0.01 0.01

5.0 10 2.25 4.5

4.95 9.95 1.5 3.0

1.4 2.9

V V

3.5 7.0

2.25 4.5

3.5 7.0

V V

0.3 1.0

1.0 2.5

0.24 0.8

mA mA

b 0.9 b 0.45

mA mA

b 1.1 b 4.0 b 0.55 b 2.5

10

Note 1: This device should not be connected to circuits with the power on because high transient voltages may cause permanent damage.

2

V V

pA

AC Electrical Characteristics* CD4007M TA e 25§ C and CL e 15 pF and rise and fall times e 20 ns. Typical temperature coefficient for all values of VDD e 0.3%/§ C Symbol

Parameter

Conditions

Typ

Max

Units

tPLH e tPHL

Propagation Delay Time


Min

35 20

60 40

ns ns

tTLH e tTHL

Transition Time


50 30

75 40

ns ns

CI

Input Capacitance

Any Input

5.0

pF

*AC Parameters may be generated by DC correlated testing.

AC Electrical Characteristics* CD4007C TA e 25§ C and CL e 15 pF and rise and fall times e 20 ns. Typical temperature coefficient for all values of VDD e 0.3%/§ C Symbol

Parameter

Conditions

Typ

Max

Units

tPLH e tPHL



Min

35 20

75 50

ns ns

tTLH e tTHL

Transition Time


50 30

100 50

ns ns

CI

Input Capacitance

Any Input

5

pF

*AC Parameters are guaranteed by DC correlated testing.

AC Test Circuits

TL/F/5943–2

TL/F/5943 – 3

TL/F/5943 – 4

Switching Time Waveforms

TL/F/5943 – 5

3

CD4007M/CD4007C Dual Complementary Pair Plus Inverter

Physical Dimensions inches (millimeters)

Ceramic Dual-In-Line Package (J) Order Number CD4007MJ or CD4007CJ NS Package Number J14A

Molded Dual-In-Line Package (N) Order Number CD4007MN or CD4007CN NS Package Number N14A

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2. A critical component is any component of a life device or system whose failure to perform can be reasonably expected to cause the failure of the life device or system, or to affect its safety or effectiveness.

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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.


CD4008BMS CMOS 4-Bit Full Adder With Parallel Carry Out

November 1994

Features

Pinout

• High-Voltage Type (20V Rating)

CD4008BMS TOP VIEW

• 4 Sum Outputs Plus Parallel Look-ahead Carry-Output • High-Speed Operation - Sum In-To-Sum Out, 160ns Typ; Carry In-To-Carry Out, 5ns Typ. At VDD = 10V, CL=50pF • Standardized Symmetrical Output Characteristics • 100% Tested For Quiescent Current At 20V • Maximum Input Current of 1µa at 18V Over Full Package-Temperature Range; - 100nA at 18V and 25oC • Noise Margin (Over Full Package Temperature Range): - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • 5V, 10V and 15V Parametric Ratings

A4 1

16 VDD

B3 2

15 B4

A3 3

14 CO

B2 4

13 S4

A2 5

12 S3

B1 6

11 S2

A1 7

10 S1

VSS 8

9 C1

Logic Diagram

• Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices”

Applications • Binary Addition/Arithmetic Units

Description CD4008BMS types consist of four full adder stages with fast look ahead carry provision from stage to stage. Circuitry is included to provide a fast “parallel-carry-out” but to permit high-speed operation in arithmetic sections using several CD4008BMS’s. CD4008BMS inputs include the four sets of bits to be added, A1 to A4 and B1 to B4, in addition to the “Carry In” bit from a previous section. CD4008BMS outputs include the four sum bits, S1 to S4. In addition to the high speed “parallel-carryout” which may be utilized at a succeeding CD4008BMS section. The CD4008BMS is supplied in these 16-lead outline packages: Braze Seal DIP H4T Frit Seal DIP H1F Ceramic Flatpack H6W

HIGH SPEED PAR CARRY

*

15

A4

*

1

B3

*

2

A3

*

3

B2

*

4

A2

*

5

B1

*

6

A1

*

7

C1

*

9

B4

CO (CARRY-OUT) 13 SUM

S4

C4 12 SUM

S3

C3 11

SUM

S2 VDD

C2 10

SUM

S1

(CARRY-IN) VSS

*ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK

VDD = 16 VSS = 8

TRUTH TABLE Ai

Bi

Ci

CO

SUM

0 1 0 1 0 1 0 1

0 0 1 1 0 0 1 1

0 0 0 0 1 1 1 1

0 0 0 1 0 1 1 1

0 1 1 0 1 0 0 1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

7-675

14

File Number

3292

Specifications CD4008BMS Absolute Maximum Ratings

Reliability Information

DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum

Thermal Resistance . . . . . . . . . . . . . . . . θja θjc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER Supply Current

SYMBOL IDD

CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND

VDD = 18V, VIN = VDD or GND Input Leakage Current

IIL

VIN = VDD or GND

VDD = 20

VDD = 18V Input Leakage Current

IIH

VIN = VDD or GND

VDD = 20

GROUP A SUBGROUPS

LIMITS TEMPERATURE

MIN

+25

-

10

µA

+125oC

-

1000

µA

3

-55oC

-

10

µA

1

+25o

C

-100

-

nA

2

+125oC

-1000

-

nA

3

-55oC

-100

-

nA

1

+25oC

-

100

nA

2

+125oC

-

1000

nA

-

100

nA

-

50

mV

-

V

3

Output Voltage

VOL15

VDD = 15V, No Load

1, 3

+25oC, +125oC, -55oC

Output Voltage

VOH15

VDD = 15V, No Load (Note 3)

1, 3

+25oC, +125oC, -55oC 14.95

Output Current (Sink)

IOL5

VDD = 5V, VOUT = 0.4V

UNITS

1

-55oC

VDD = 18V

MAX

2

oC

1

+25oC

0.53

-

mA


IOL10


1

+25oC

1.4

-

mA


IOL15


1

+25oC

3.5

-

mA

1

+25oC

-

-0.53

mA

1

+25oC

-

-1.8

mA

Output Current (Source) Output Current (Source)

IOH5A IOH5B

VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V

Output Current (Source)

IOH10


1

+25oC

-

-1.4

mA


IOH15

VDD = 15V, VOUT = 13.5V

1

+25oC

-

-3.5

mA

1

+25oC

-2.8

-0.7

V

1

+25oC

0.7

2.8

V

N Threshold Voltage P Threshold Voltage Functional

VNTH VPTH F

VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VDD = 2.8V, VIN = VDD or GND

7

+25oC

VDD = 20V, VIN = VDD or GND

7

+25oC


8A

+125oC


8B

-55oC

VOH > VOL < VDD/2 VDD/2

V

Input Voltage Low (Note 2)

VIL

VDD = 5V, VOH > 4.5V, VOL < 0.5V

1, 2, 3

+25oC, +125oC, -55oC

-

1.5

V

Input Voltage High (Note 2)

VIH

VDD = 5V, VOH > 4.5V, VOL < 0.5V

1, 2, 3

+25oC, +125oC, -55oC

3.5

-

V

Input Voltage Low (Note 2)

VIL

VDD = 15V, VOH > 13.5V, VOL < 1.5V

1, 2, 3

+25oC, +125oC, -55oC

-

4

V

Input Voltage High (Note 2)

VIH

VDD = 15V, VOH > 13.5V, VOL < 1.5V

1, 2, 3

+25oC, +125oC, -55oC

11

-

V

NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs

7-676

3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max.

Specifications CD4008BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER Propagation Delay Sum In to Sum Out

SYMBOL TPHL1 TPLH1

CONDITIONS (NOTE 1, 2) VDD = 5V, VIN = VDD or GND

TPHL2 TPLH2


Propagation Delay Sum In To Carry Out

TPHL3 TPLH3


Transition Time

9 10, 11

Propagation Delay Carry In To Cum Out

Propagation Delay Carry In To Carry Out

GROUP A SUBGROUPS TEMPERATURE

9 10, 11 9 10, 11

TPHL4 TPLH4


TTHL TTLH


9 10, 11

+25oC +125oC,

-55oC

+25oC +125oC,

-55oC

+25oC +125oC,

-55oC

+25oC +125oC,

-55oC

LIMITS MIN

MAX

UNITS

-

800

ns

-

1080

ns

-

740

ns

-

999

ns

-

400

ns

-

540

ns

-

200

ns

-

270

ns

9

+25oC

-

200

ns

10, 11

+125oC, -55oC

-

270

ns

NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current

SYMBOL

CONDITIONS

NOTES

TEMPERATURE

MIN

MAX

UNITS

IDD


1, 2

-55oC, +25oC

-

5

µA

+125oC

-

150

µA



Output Voltage

VOL

VDD = 5V, No Load

1, 2

1, 2

1, 2

-55 C, +25 C

-

10

µA

+125oC

-

300

µA

o

o

-

10

µA

+125oC

-

600

µA

+25oC, +125oC,

-

50

mV

-55oC,

+25oC

-55oC Output Voltage

VOL

VDD = 10V, No Load

1, 2

+25oC, +125oC, -55oC

-

50

mV

Output Voltage

VOH

VDD = 5V, No Load

1, 2

+25oC, +125oC, -55oC

4.95

-

V

Output Voltage

VOH

VDD = 10V, No Load

1, 2

+25oC, +125oC, -55oC

9.95

-

V


IOL5


1, 2

+125oC

0.36

-

mA

-55oC

0.64

-

mA

+125oC

0.9

-

mA

-55oC

1.6

-

mA

+125oC

2.4

-

mA

-55oC

4.2

-

mA





IOL10

IOL15

IOH5A

IOH5B


1, 2


1, 2


1, 2


1, 2

7-677

+125oC

-

-0.36

mA

-55oC

-

-0.64

mA

+125oC

-

-1.15

mA

-55oC

-

-2.0

mA

Specifications CD4008BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER

SYMBOL


IOH10

CONDITIONS VDD = 10V, VOUT = 9.5V

NOTES

TEMPERATURE

MIN

MAX

UNITS

1, 2

+125oC

-

-0.9

mA

-55 C

-

-1.6

mA

+125oC

-

-2.4

mA

-

-4.2

mA

-

3

V

o


IOH15

VDD =15V, VOUT = 13.5V

1, 2

-55 Input Voltage Low

VIL

VDD = 10V, VOH > 9V, VOL < 1V

1, 2

oC

+25oC, +125oC, -55oC

Input Voltage High

VIH

VDD = 10V, VOH > 9V, VOL < 1V

+25oC, +125oC, -55oC

+7

-

V

1, 2, 3

+25oC

-

320

ns

Propagation Delay Sum In To Sum Out

TPHL1 TPLH1

VDD = 15V

1, 2, 3

+25 C

-

230

ns

Propagation Delay Carry In To Sum Out

TPHL2 TPLH2

VDD = 10V

1, 2, 3

+25oC

-

310

ns

VDD = 15V

1, 2, 3

+25oC

-

230

ns

Propagation Delay Sum In To Carry Out

TPLH3 TPHL3

VDD = 10V

1, 2, 3

+25oC

-

180

ns

1, 2, 3

+25oC

-

130

ns

Propagation Delay Carry In To Carry Out Transition Time

Input Capacitance

TPHL4 TPLH4 TTHL TTLH CIN

VDD = 10V

1, 2

VDD = 15V

o

o

VDD = 10V

1, 2, 3

+25 C

-

100

ns

VDD = 15V

1, 2, 3

+25oC

-

80

ns

1, 2, 3

+25oC

-

100

ns

1, 2, 3

oC

-

80

ns

+25oC

-

7.5

pF

VDD = 10V VDD = 15V Any Input

1, 2

+25

NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current

SYMBOL IDD

CONDITIONS

NOTES


TEMPERATURE

MIN

MAX

UNITS

1, 4

+25o

-

25

µA

C

N Threshold Voltage

VNTH

VDD = 10V, ISS = -10µA

1, 4

+25oC

-2.8

-0.2

V

N Threshold Voltage Delta

∆VNTH

VDD = 10V, ISS = -10µA

1, 4

+25oC

-

±1

V

P Threshold Voltage

VPTH

VSS = 0V, IDD = 10µA

1, 4

+25oC

0.2

2.8

V

P Threshold Voltage Delta

∆VPTH

VSS = 0V, IDD = 10µA

1, 4

+25oC

-

±1

V

1

+25oC

VOH > VDD/2

VOL < VDD/2

V

Functional

F

VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND

7-678

Specifications CD4008BMS TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER

SYMBOL


TPHL TPLH

CONDITIONS VDD = 5V

NOTES

TEMPERATURE

MIN

MAX

UNITS

1, 2, 3, 4

+25oC

-

1.35 x +25oC Limit

ns

3. See Table 2 for +25oC limit.

NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

4. Read and Record

TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC PARAMETER

SYMBOL

DELTA LIMIT

Supply Current - MSI-2

IDD

± 1.0µA


IOL5

± 20% x Pre-Test Reading

IOH5A

± 20% x Pre-Test Reading


TABLE 6. APPLICABLE SUBGROUPS MIL-STD-883 METHOD

GROUP A SUBGROUPS

Initial Test (Pre Burn-In)

100% 5004

1, 7, 9

IDD, IOL5, IOH5A

Interim Test 1 (Post Burn-In)

100% 5004

1, 7, 9

IDD, IOL5, IOH5A

Interim Test 2 (Post Burn-In)

100% 5004

1, 7, 9

IDD, IOL5, IOH5A

100% 5004

1, 7, 9, Deltas

100% 5004

1, 7, 9

100% 5004

1, 7, 9, Deltas

100% 5004

2, 3, 8A, 8B, 10, 11

CONFORMANCE GROUP

PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A Group B

IDD, IOL5, IOH5A

Sample 5005

1, 2, 3, 7, 8A, 8B, 9, 10, 11

Subgroup B-5

Sample 5005

1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas

Subgroup B-6

Sample 5005

1, 7, 9

Sample 5005

1, 2, 3, 8A, 8B, 9

Group D

READ AND RECORD

Subgroups 1, 2, 3, 9, 10, 11

Subgroups 1, 2 3

NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.

TABLE 7. TOTAL DOSE IRRADIATION

CONFORMANCE GROUPS Group E Subgroup 2

TEST

READ AND RECORD

MIL-STD-883 METHOD

PRE-IRRAD

POST-IRRAD

PRE-IRRAD

POST-IRRAD

5005

1, 7, 9

Table 4

1, 9

Table 4

TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION

OPEN

GROUND

VDD

Static Burn-In 1 Note 1

10 - 14

1 - 9, 15

16

Static Burn-In 2 Note 1

10 - 14

8

1 - 7, 9, 15, 16

Dynamic BurnIn Note 1

-

8

16

10 - 14

8

1 - 7, 9, 15, 16

Irradiation Note 2

7-679

9V ± -0.5V

50kHz

25kHz

10 - 14

2, 4, 6, 15

1, 3, 5, 7, 9

Specifications CD4008BMS TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION

OPEN

GROUND

VDD

9V ± -0.5V

50kHz

25kHz

NOTE: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V

Typical Propagation Delay CO A13 - 16 B13 - 16

CD4008

S13 - 16

50 + 50 + 90 + 155

2(50) + 90 + 155 2(Ci - CO) + (Si - CO) + (Ci - SO) = 345

S9 - 12

50 + 90 + 155

50 90 155 (Ci - CO) + (Si - CO) + (Ci - SO)

S5 - 8

90 + 155

(Si - CO) + (Ci - SO) =90 + 155

S1 - 4

160

(Si - SO)

Ci CO A9 - 12 B9 - 12

CD4008 Ci CO

A5 - 8 A5 - 8

CD4008 Ci CO

A1 - 4 B1 - 4

CD4008 Ci VSS

ALL SUMS SETTLED AFTER 345ns

FIGURE 1. PROPAGATION DELAY FOR A 16 BIT ADDER (10V OPERATION)

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240

EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05

680

ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029

CD4008BMS

AMBIENT TEMPERATURE (TA) = +25oC

SUPPLY VOLTAGE (VDD) = 5V

400

300 10V 200 15V 100

0

20

40 60 80 100 120 LOAD CAPACITANCE (CL) (pF)

SUM-IN TO CARRY-OUT PROPAGATION DELAY TIME (tPHL, tPLH) (ns)

CARRY-IN TO CARRY-OUT PROPAGATION DELAY TIME (tPHL, tPLH) (ns)

400

300 10V 200 15V 100

20


GATE-TO-SOURCE VOLTAGE (VGS) = -5V

0 -5 -10 -15

-10V

-20 -25

-15V

-30

15V

50

25

20


140


300

SUPPLY VOLTAGE (VDD) = 5V 250

200

150

10V 15V

100

50

20


140

FIGURE 5. TYPICAL SUM-IN TO CARRY-OUT PROPAGATION DELAY TIME vs LOAD CAPACITANCE DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)


0

10V

0

140

FIGURE 4. TYPICAL CARRY-IN TO SUM-OUT PROPAGATION DELAY TIME vs LOAD CAPACITANCE DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5

75

FIGURE 3. TYPICAL CARRY-IN TO CARRY-OUT PROPAGATION DELAY TIME vs LOAD CAPACITANCE


0

100

0


500


125

140

FIGURE 2. TYPICAL SUM-IN TO SUM-OUT PROPAGATION DELAY TIME vs LOAD CAPACITANCE

600


150

0

0

GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5

-10V

-15V

FIGURE 6. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS

-10

-15

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

500

CARRY-IN TO CARRY-OUT PROPAGATION DELAY TIME (tPHL, tPLH) (ns)

SUM-IN TO SUM-OUT PROPAGATION DELAY TIME (tPHL, tPLH) (ns)

Typical Performance Characteristics

FIGURE 7. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS

7-681

CD4008BMS (Continued)


30

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

OUTPUT LOW (SINK) CURRENT (IOL) (mA)


GATE-TO-SOURCE VOLTAGE (VGS) = 15V

25 20 15

10V

10 5

5V 0


15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0

5.0 2.5

5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

POWER DISSIPATION/PACKAGE (PD) (µW)

5V 0

5

10

15

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

FIGURE 8. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS 106

10V

7.5

FIGURE 9. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS


105 SUPPLY VOLTAGE (VDD) = 15V 104

10V

103 5V 102

5V 3.5V

10 LOAD CAPACITANCE (CL) = 15pF (CL) = 50pF 1

10

102

103

104

INPUT FREQUENCY (fφ) (kHz)

FIGURE 10. TYPICAL DISSIPATION CHARACTERISTICS

Chip Dimensions and Pad Layouts

METALLIZATION: Thickness: 11kÅ − 14kÅ, IVATION: BOND PADS:

10.4kÅ - 15.6kÅ, Silane 0.004 inches X 0.004 inches MIN

DIE THICKNESS:

Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch)

7-682

AL.

0.0198 inches - 0.0218 inches






























CD4016BM/CD4016BC Quad Bilateral Switch General Description The CD4016BM/CD4016BC is a quad bilateral switch intended for the transmission or multiplexing of analog or digital signals. It is pin-for-pin compatible with CD4066BM/ CD4066BC.

Features Y Y Y Y

Y

Y

Wide supply voltage range 3V to 15V Wide range of digital and analog switching g 7.5 VPEAK ‘‘ON’’ resistance for 15V operation 400X (typ.) Matched ‘‘ON’’ resistance over 15V signal input DRON e 10X (typ.) High degree of linearity 0.4% distortion (typ.) @ f IS e 1 kHz, VIS e 5 Vp-p, VDDbVSS e 10V, RL e 10 kX Extremely low ‘‘OFF’’ switch leakage 0.1 nA (typ.) @ V DD b VSS e 10V TA e 25§ C

Y Y

Y

Extremely high control input impedance 1012X (typ.) b 50 dB (typ.) Low crosstalk between switches @ f e 0.9 MHz, R e 1 kX IS L Frequency response, switch ‘‘ON’’ 40 MHz (typ.)

Applications Y

Y Y Y Y

Analog signal switching/multiplexing # Signal gating # Squelch control # Chopper # Modulator/Demodulator # Commutating switch Digital signal switching/multiplexing CMOS logic implementation Analog-to-digital/digital-to-analog conversion Digital control of frequency, impedance, phase, and analog-signal gain

Schematic and Connection Diagrams Dual-In-Line Package

TL/F/5661 – 1

Order Number CD4016B


TL/F/5661


CD4016BM/CD4016BC Quad Bilateral Switch

August 1989

Absolute Maximum Ratings

Recommended Operating Conditions (Note 2)

If Military/Aerospace specified devices are required, please the National Semiconductor Sales Office/Distributors for availability and specifications.

VDD Supply Voltage VIN Input Voltage TA Operating Temperature Range CD4016BM CD4016BC

(Notes 1 and 2) VDD Supply Voltage

b 0.5V to a 18V b 0.5V to VDD a 0.5V VIN Input Voltage b 65§ C to a 150§ C TS Storage Temperature Range Power Dissipation (PD) Dual-In-Line 700 mW Small Outline 500 mW Lead Temperature (Soldering, 10 seconds) 260§ C

3V to 15V 0V to VDD b 55§ C to a 125§ C b 40§ C to a 85§ C

DC Electrical Characteristics CD4016BM (Note 2) Symbol

Parameter

b 55§ C

Conditions

Min IDD


VDD e 5V, VIN e VDD or VSS VDD e 10V, VIN e VDD or VSS VDD e 15V, VIN e VDD or VSS

Max

25§ C Min

125§ C Min

Units

Typ

Max

Max

0.25 0.5 1.0

0.01 0.01 0.01

0.25 0.5 1.0

7.5 15 30

mA mA mA

600 360

250 200

660 400

960 600

X X

1870 775

850 400

2000 850

2600 1230

X X

Signal Inputs and Outputs RON

DRON

IIS

‘‘ON’’ Resistance

D‘‘ON’’ Resistance Between any 2 of 4 Switches (In Same Package) Input or Output Leakage Switch ‘‘OFF’’

VDDbVSS 2 VC e VDD, VIS e VSS or VDD VDD e 10V VDD e 15V VDDbVSS RL e 10 kX to 2 VC e VDD VDD e 10V, VIS e 4.75 to 5.25V VDD e 15V, VIS e 7.25 to 7.75V RL e 10 kX to

VDDbVSS 2 VC e VDD, VIS e VSS to VDD VDD e 10V VDD e 15V RL e 10 kX to

15 10

VC e 0, VDD e 15V VIS e 15V and 0V, VOS e 0V and 15V

g 50

g 0.1

X X g 50

g 500

nA

0.7 0.7 0.7

0.5 0.5 0.5

V V V

Control Inputs VILC

VIHC

IIN

Low Level Input Voltage

High Level Input Voltage

Input Current

VIS e VSS and VDD VOS e VDD and VSS IIS e g 10 mA VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V

0.9 0.9 0.9

(see Note 6 and Figure 8 )

VDDbVSS e 15V VDDtVIStVSS VDDtVCtVSS

3.5 7.0 11.0

3.5 7.0 11.0 g 0.1

2

3.5 7.0 11.0 g 10 b 5

g 0.1

V V V g 1.0

mA

DC Electrical Characteristics CD4016BC (Note 2) (Continued) Symbol

Parameter

b 40§ C

Conditions

Min IDD



Max

25§ C Min

85§ C Min

Units

Typ

Max

Max

1.0 2.0 4.0

0.01 0.01 0.01

1.0 2.0 4.0

7.5 15 30

mA mA mA

610 370

275 200

660 400

840 520

X X

1900 790

850 400

2000 850

2380 1080

X X

Signal Inputs and Outputs RON

DRON

‘‘ON’’ Resistance

D‘‘ON’’ Resistance Between any 2 of 4 Switches (In Same Package)

IIS

Input or Output Leakage Switch ‘‘OFF’’

VDDbVSS 2 VC e VDD, VIS e VSS or VDD VDD e 10V VDD e 15V VDDbVSS RL e 10 kX to 2 VC e VDD e e VDD 10V, VIS 4.75 to 5.25V VDD e 15V, VIS e 7.25 to 7.75V RL e 10 kX to

VDDbVSS 2 VC e VDD, VIS e VSS to VDD VDD e 10V VDD e 15V RL e 10 kX to

15 10

VC e 0, VDD e 15V VIS e 0V or 15V, VOS e 15V or 0V

g 50

g 0.1

X X g 50

g 200

nA

0.7 0.7 0.7

0.4 0.4 0.4

V V V

Control Inputs VILC

VIHC

IIN



Input Current

VIS e VSS and VDD VOS e VDD and VSS IIS e g 10 mA VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V

0.9 0.9 0.9

(see Note 6 and Figure 8 )

3.5 7.0 11.0

VCCbVSS e 15V VDDtVIStVSS VDDtVCtVSS

3.5 7.0 11.0 g 0.3

3.5 7.0 11.0 g 10 b 5

g 0.3

V V V g 1.0

mA

AC Electrical Characteristics* TA e 25§ C, tr e tf e 20 ns and VSS e 0V unless otherwise specified Symbol

Parameter

tPHL, tPLH

Propagation Delay Time Signal Input to Signal Output

tPZH, tPZL

tPHZ, tPLZ

Typ

Max

Units

VC e VDD, CL e 50 pF, (Figure 1 ) RL e 200k VDD e 5V VDD e 10V VDD e 15V

58 27 20

100 50 40

ns ns ns

Propagation Delay Time Control Input to Signal Output High Impedance to Logical Level

RL e 1.0 kX, CL e 50 pF, (Figures 2 and 3 ) VDD e 5V VDD e 10V VDD e 15V

20 18 17

50 40 35

ns ns ns

Propagation Delay Time Control Input to Signal Output Logical Level to High Impedance

RL e 1.0 kX, CL e 50 pF, (Figures 2 and 3 ) VDD e 5V VDD e 10V VDD e 15V VC e VDD e 5V, VSS eb5 RL e 10 kX, VIS e 5 VP-P, f e 1 kHz, (Figure 4 )

15 11 10 0.4

40 25 22

ns ns ns %

Sine Wave Distortion

Conditions

3

Min

AC Electrical Characteristics* (Continued) TA e 25§ C, tr e tf e 20 ns and VSS e 0V unless otherwise specified Symbol

Parameter Frequency Response Ð Switch ‘‘ON’’ (Frequency at b3 dB)

Feedthrough Ð Switch ‘‘OFF’’ (Frequency at b50 dB)

Crosstalk Between Any Two Switches (Frequency at b50 dB)

Crosstalk; Control Input to Signal Output Maximum Control Input

Conditions

Min

VC e VDD e 5V, VSS eb5V, RL e 1 kX, VIS e 5 VP-P, 20 Log10 VOS/VOS (1 kHz) bdB, (Figure 4 ) VDD e 5V, VC e VSS eb5V, RL e 1 kX, VIS e 5 VP-P, 20 Log10 (VOS/VIS) eb50 dB, (Figure 4 ) VDD e VC(A) e 5V; VSS e VC(B) eb5V, RL e 1 kXVIS(A) e 5 VP-P, 20 Log10 (VOS(B)/VOS(A) ) eb50 dB, (Figure 5 ) VDD e 10V, RL e 10 kX RIN e 1 kX, VCC e 10V Square Wave, CL e 50 pF (Figure 6 ) RL e 1 kX, CL e 50 pF, (Figure 7 ) VOS(f) e (/2 VOS(1 kHz) VDD e 5V VDD e 10V VDD e 15V

CIS

Signal Input Capacitance

COS

Signal Output Capacitance

VDD e 10V

CIOS

Feedthrough Capacitance

VC e 0V

CIN

Control Input Capacitance

Typ

Max

Units

40

MHz

1.25

MHz

0.9

MHz

150

mVP-P

6.5 8.0 9.0

MHz MHz MHz

4

pF

4

pF

0.2 5

pF 7.5

pF

*AC Paramters are guaranteed by DC correlated testing. Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The tables of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provide conditions for actual device operation. Note 2: VSS e 0V unless otherwise specified. Note 3: These devices should not be connected to circuits with the power ‘‘ON’’. Note 4: In all cases, there is approximately 5 pF of probe and jig capacitance on the output; however, this capacitance is included in CL wherever it is specified. Note 5: VIS is the voltage at the in/out pin and VOS is the voltage at the out/in pin. VC is the voltage at the control input. Note 6: If the switch input is held at VDD, VIHC is the control input level that will cause the switch output to meet the standard ‘‘B’’ series VOH and IOH output levels. If the analog switch input is connected to VSS, VIHC is the control input level Ð which allows the switch to sink standard ‘‘B’’ series l IOH l , high level current, and still maintain a VOL s ‘‘B’’ series. These currents are shown in Figure 8 .

AC Test Circuits and Switching Time Waveforms

Figure 1. tPLH, tPLH Propagation Delay Time Signal Input to Signal Output

TL/F/5661 – 2

FIGURE 2. tPZH, tPHZ Propagation Delay Time Control to Signal Output

4

AC Test Circuits and Switching Time Waveforms (Continued)

FIGURE 3. tPZH, tPHZ Propagation Delay Time Control to Signal Output

VC e VDD for distortion and frequency response tests VC e VSS for feedthrough test

FIGURE 4. Sine Wave Distortion, Frequency Response and Feedthrough

FIGURE 5. Crosstalk Between Any Two Switches

TL/F/5661 – 3

FIGURE 6. Crosstalk Ð Control to Input Signal Output

5

AC Test Circuits and Switching Time Waveforms (Continued)

TL/F/5661 – 4

FIGURE 7. Maximum Control Input Frequency

Temperature Range

MILITARY

COMMERCIAL

Switch Input VDD

VIS

5 5 10 10 15 15

0 5 0 10 0 15

5 5 10 10 15 15

0 5 0 10 0 15

Switch Output VOS(V)

IIS (mA) TLOW

25§ C

THIGH

0.25 b 0.25 0.62 b 0.62 1.8 b 1.8

0.2 b 0.2 0.5 b 0.5 1.5 b 1.5

0.14 b 0.14 0.35 b 0.35 1.1 b 1.1

0.2

0.16

0.12

b 0.2

b 0.16

b 0.12

0.5

0.4

0.3

b 0.5

b 0.4

b 0.3

1.4

1.2

1.0

b 1.4

b 1.2

b 1.0

Min

Max 0.4

4.6 0.5 9.5 1.5 13.5 0.4 4.6 0.5 9.5 1.5 13.5

FIGURE 8. CD4016B Switch Test Conditions for VIHC

Typical Performance Characteristics ‘ON’ Resistance vs. Signal Voltage TA e 25§ C

‘ON’ Resistance Temperature Variation for VDDbVSS e 10V

‘ON’ Resistance Temperature Variation for VDDbVSS e 15V

TL/F/5661 – 5

6

Typical Applications 4 Input Multiplexer

Sample/Hold Amplifier

TL/F/5661 – 6

Special Considerations supply voltages, s5V, the CD4016B’s on resistance becomes non-linear. It is recommended that at 5V, voltages on the in/out pins be maintained within about 1V of either VDD or VSS; and that at 3V the voltages on the in/out pins should be at VDD or VSS for reliable operation.

The CD4016B is composed of 4, two-transistor analog switches. These switches do not have any linearization or compensation circuitry for ‘‘RON’’ as do the CD4066B’s. Because of this, the special operating considerations for the CD4066B do not apply to the CD4016B, but at low

7

CD4016BM/CD4016BC Quad Bilateral Switch


Dual-In-Line Package Order Number CD4016CJ or CD4016MJ NS Package J14A

Dual-In-Line Package Order Number CD4016CN NS Package N14A NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: LIFE POLICY

1. Life devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the . National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018















CD4002M/CD4002C Dual 4-Input NOR Gate CD4012M/CD4012C Dual 4-Input NAND Gate General Description

Features

These NOR and NAND gates are monolithic complementary MOS (CMOS) integrated circuits. The N- and P-channel enhancement mode transistors provide a symmetrical circuit with output swings essentially equal to the supply voltage. This results in high noise immunity over a wide supply voltage range. No DC power other than that caused by leakage current is consumed during static conditions. All inputs are protected against static discharge and latching conditions.

Y Y Y

Wide supply voltage range Low power High noise immunity

3.0V to 15V 10 nW (typ.) 0.45 VDD (typ.)

Applications Y Y Y Y

Automotive Data terminals Instrumentation Medical Electronics

Y Y Y Y

Alarm system Industrial controls Remote metering Computers

Connection Diagrams CD4012 Dual-In-Line Package

CD4002 Dual-In-Line Package

TL/F/5940 – 1

Top View

TL/F/5940 – 2

Top View Order Number CD4002 or CD4012


TL/F/5940


CD4002M/CD4002C Dual 4-Input NOR Gate CD4012M/CD4012C Dual 4-Input NAND Gate

March 1988

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please the National Semiconductor Sales Office/Distributors for availability and specifications. Voltage at Any Pin Operating Temperature Range CD4002M, CD4012M CD4002C, CD4012C

Storage Temperature Range (TS) Power Dissipation (PD) Dual-In-Line Small Outline Operating Range (VDD)

VSS b0.3V to VDD a 0.3V b 55§ C to a 125§ C b 40§ C to a 85§ C

b 65§ C to a 150§ C

700 mW 500 mW VSS a 3.0V to VSS a 15V

Lead Temperature (TL) (Soldering, 10 seconds)

260§ C

DC Electrical Characteristics CD4002M, CD4012M Limits Symbol

Parameter

b 55§ C

Conditions

Min

Max

a 25§ C

Min

Typ

a 125§ C

Max

Min

Units

Max

IDD



0.05 0.1

0.001 0.05 0.001 0.1

3.0 6

mA mA

PD

Quiescent Device VDD e 5.0V Dissipation/Package VDD e 10V

0.25 1.0

0.005 0.25 0.01 1.0

15 60

mW mW

VOL


0.05 0.05

0.05 0.05

V V

VOH


VDD e 5.0V, VI e VDD, IO e 0A VDD e 10V, VI e VDD, IO e 0A VDD e 5.0V, VI e VSS, IO e 0A VDD e 10V, VI e VSS, IO e 0A

0 0

4.95 9.95

4.95 9.95

5.0 10

4.95 9.95

V V

VNL


VDD e 5.0V, VO e 3.6V, IO e 0A VDD e 10V, VO e 7.2V, IO e 0A

1.5 3.0

1.5 3.0

2.25 4.5

1.4 2.9

V V

VNH


VDD e 5.0V, VO e 0.95V, IO e 0A VDD e 10V, VO e 2.9V, IO e 0A

1.4 2.9

1.5 3.0

2.25 4.5

1.5 3.0

V V

IDN

Output Drive Current N-Channel (4002) (Note 2)

VDD e 5.0V, VO e 0.4V, VI e VDD VDD e 10V, VO e 0.5V, VI e VDD

0.5 1.1

0.40 0.9

1.0 2.5

0.28 0.65

mA mA

IDP

Output Drive Current P-Channel (4002) (Note 2)

VDD e 5.0V, VO e 2.5V, VI e VSS VDD e 10V, VO e 9.5V, VI e VSS

b 0.62 b 0.62

b 0.5 b 0.5

b 2.0 b 1.0

b 0.35 b 0.35

mA mA

IDN



0.31 0.63

0.25 0.5

0.5 0.6

0.175 0.35

mA mA

IDP



b 0.31 b 0.75

b 0.25 b 0.6

b 0.5 b 1.2

b 0.175 b 0.4

mA mA

II

Input Current

10

0.05 0.05

pA

Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation. Note 2: IDN and IDP are tested one output at a time.

2

DC Electrical Characteristics CD4002C, CD4012C Limits Symbol

Parameter

b 55§ C

Conditions

Min

Max

a 25§ C

Min

a 85§ C

Typ

Max

Min

Units

Max

IDD



0.5 5.0

0.005 0.005

0.5 5.0

15 30

mA mA

PD

Quiescent Device VDD e 5.0V Dissipation/Package VDD e 10V

2.5 50

0.025 0.05

2.5 50

75 300

mW mW

VOL


0.05 0.05

0 0

0.05 0.05

0.05 0.05

V V

VOH


VNL


VNH


IDN

VDD e 5.0V, VI e VDD, IO e 0A VDD e 10V, VI e VDD, IO e 0A VDD e 5.0V, VI e VSS, IO e 0A VDD e 10V, VI e VSS, IO e 0A

4.95 9.95

4.95 9.95

5.0 10

4.95 9.95

V V

VDD e 5.0V, VO t 3.6V, IO e 0A VDD e 10V, VO t 7.2V, IO e 0A VDD e 5.0V, VO s 0.95V, IO e 0A VDD e 10V, VO s 2.9V, IO e 0A

1.5 3.0

1.5 3.0

2.25 4.5

1.4 2.9

V V

1.4 2.9

1.5 3.0

2.25 4.5

1.5 3.0

V V



0.35 0.72

0.3 0.6

1.0 2.5

0.24 0.48

mA mA

IDN



0.145 0.3

0.12 0.25

0.5 0.6

0.095 0.2

mA mA

IDP



b 0.35 b 0.3

b 0.3 b 0.25

b 2.0 b 1.0

b 0.24 b 0.2

mA mA

IDP



b 0.145 b 0.35

b 0.12 b 0.3

b 0.5 b 1.2

b 0.095 b 0.24

mA mA

II

Input Current

10

pA

Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation. Note 2: IDN and IDP are tested one output at a time.

3

AC Electrical Characteristics* TA e 25§ C, CL e 15 pF, and input rise and fall times e 20 ns. Typical temperature coefficient for all values of VDD e 0.3%/§ C. Symbol

Parameter

Conditions

tPHL

Propagation Delay Time High to Low Level

tPLH

Min

Typ

Max

Units


35 25

50 40

ns ns

Propagation Delay Time Low to High Level


35 25

50 40

ns ns

tTHL

Transition Time High to Low Level


65 35

175 75

ns ns

tTLH

Transition Time Low to High Level


65 35

125 70

ns ns

CIN

Input Capacitance

Any Input

5.0

tPHL



35 25

120 65

ns ns

TPLH



35 25

80 55

ns ns

tTHL



65 35

300 125

ns ns

tTLH



65 35

200 115

ns ns

CIN

Input Capacitance

Any Input

5.0

CD4002M

pF

CD4002C

pF


AC Electrical Characteristics* TA e 25§ C, CL e 15 pF, and input rise and fall times e 20 ns. Typical temperature coefficient for all values of VDD e 0.3%/§ C. Symbol

Parameter

Conditions

tPHL


tPLH

Min

Typ

Max

Units


50 25

75 40

ns ns



50 25

75 40

ns ns

tTHL



75 50

125 75

ns ns

tTLH



75 40

100 60

ns ns

CIN

Input Capacitance

Any Input

5.0

tPHL



50 25

100 50

ns ns

TPLH



50 25

100 50

ns ns

tTHL



75 50

150 100

ns ns

tTLH



75 40

125 75

ns ns

CIN

Input Capacitance

Any Input

5.0

CD4012M

pF

CD4012C

pF

*AC Parameters are guaranteed by DC correlated testing. Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation.

4


Ceramic Dual-In-Line Package (J) Order Number CD4002MJ, CD4002CJ, CD4012MJ or CD4012CJ NS Package Number J14A

5

CD4002M/CD4002C Dual 4-Input NOR Gate CD4012M/CD4012C Dual 4-Input NAND Gate

Physical Dimensions inches (millimeters) (Continued)

Molded Dual-In-Line Package (N) Order Number CD4002MN, CD4002CN, CD4012MN or CD4012CN NS Package Number N14A








Revised January 1999

CD4021BC 8-Stage Static Shift General Description The CD4021BC is an 8-stage parallel input/serial output shift . A parallel/serial control input enables individual JAM inputs to each of 8 stages. Q outputs are available from the sixth, seventh, and eighth stages. All outputs have equal source and sink current capabilities and conform to standard “B” series output drive. When the parallel/serial control input is in the logical “0” state, data is serially shifted into the synchronously with the positive transition of the clock. When the parallel/ serial control is in the logical “1” state, data is jammed into each stage of the asynchronously with the clock.

All inputs are protected against static discharge with diodes to VDD and VSS.

Features ■ Wide supply voltage range: ■ High noise immunity:

3.0V to 15V

0.45 VDD (typ.)

■ Low power TTL compatibility: Fan out of 2 driving 74L or 1 driving 74LS ■ 5V–10V–15V parametric ratings ■ Symmetrical output characteristics ■ Maximum input leakage 1 µA at 15V over full temperature range

Ordering Code: Order Number

Order Code

Package Description

CD4021BCM

M16A

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body

CD4021BCN

N16E

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Truth Table

Pin Assignments for DIP and SOIC

CL Serial (Note 1) Input

Parallel/ Qn Q1 Serial PI 1 PI n (Internal) (Note 2) Control

X

X

1

0

0

0

0

X

X

1

0

1

0

1

X

X

1

1

0

1

0

X

1

1

1

1

1

0

0

X

X

0

Qn−1

1

0

X

X

1

Qn−1

X

0

X

X

Q1

Qn

X

X = Don't care case Note 1: Level change Note 2: No change

Top View

© 1999 Fairchild Semiconductor Corporation

DS005954.prf

www.fairchildsemi.com

CD4021BC 8-Stage Static Shift

October 1987

CD4021BC

Logic Diagram


2


−0.5V to +18V

Supply Voltage (VDD) Input Voltage (VIN)

Supply Voltage (VDD)

−0.5V to VDD +0.5V −65°C to +150°C

Storage Temperature Range (TS)

700 mW

Small Outline

500 mW

(Soldering, 10 seconds)

Note 3: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation.

260°C

DC Electrical Characteristics

VOL

Parameter

Note 4: VSS = 0V unless otherwise specified.

(Note 4) −40°C

Conditions

Min

IOL

IOH

IIN

+85°C

Typ

Max

Min

Max

Units

20

0.1

20

150

µA

Current

VDD = 10V, VIN = VDD or VSS

40

0.2

40

300

µA


80

0.3

80

600

µA

0.05

0

0.05

0.05

V

0.05

0

0.05

0.05

V

0.05

0

0.05

0.05

V

LOW Level

VDD = 5V

Output Voltage

VDD = 10V

HIGH Level

VDD = 5V

Output Voltage

VDD = 10V

LOW Level Input Voltage

VIH

+25°C Min


|IO| < 1 µA

|IO|< 1 µA

VDD = 15V VIL

Max

Quiescent Device

VDD = 15V VOH

−40°C to +85°C

CD4021BCN

Dual-In-Line Lead Temperature (TL)

IDD

0 to VDD

Operating Temperature Range (TA)

Power Dissipation (PD)

Symbol

3V to 15V

Input Voltage (VIN)

4.95

4.95

5

4.95

V

9.95

9.95

10

9.95

V

14.95

14.95

15

14.95

VDD = 5V, VO = 0.5V or 4.5V

1.5

2

V

1.5

1.5

V

VDD = 10V, VO = 1.0V or 9.0V

3.0

4

3.0

3.0

V

VDD = 15V, VO = 1.5V or 13.5V

4.0

6

4.0

4.0

V

HIGH Level

VDD = 5V, VO = 0.5V or 4.5V

3.5

3.5

3

3.5

V

Input Voltage

VDD = 10V, VO = 1.0V or 9.0V

7.0

7.0

6

7.0

V

VDD = 15V, VO = 1.5V or 13.5V

11.0

11.0

9

11.0

V

LOW Level Output

VDD = 5V, VO = 0.4V

0.52

0.44

0.88

0.36

mA

Current (Note 5)

VDD = 10V, VO = 0.5V

1.3

1.1

2.2

0.90

mA

VDD = 15V, VO = 1.5V

3.6

3.0

8

2.4

mA

HIGH Level Output

VDD = 5V, VO = 4.6V

−0.52

−0.44

−0.88

−0.36

mA

Current (Note 5)

VDD = 10V, VO = 9.5V

−1.3

−1.1

−2.2

−0.90

mA

VDD = 15V, VO = 13.5V

−3.6

−3.0

−8

−2.4

mA

Input Current

VDD = 15V, VIN = 0V

−0.3

−10−5

−0.3

−1.0

µA

VDD = 15V, VIN = 15V

0.3

10−5

0.3

1.0

µA

Note 5: IOH and IOL are tested one output at a time.

3


CD4021BC

Absolute Maximum Ratings(Note 3) (Note 4)

CD4021BC

AC Electrical Characteristics

(Note 6)

TA = 25°C, input tr, tf = 20 ns, CL = 50 pF, RL = 200 kΩ Symbol tPLH, tPHL

tTHL, tTLH

fCL

tW

trCL, tfCL

ts

Parameter Propagation Delay Time

Transition Time

Conditions

Min

Max

Units

240

350

ns

VDD = 10V

100

175

ns

VDD = 15V

70

140

ns

VDD = 5V

100

200

ns

VDD = 10V

50

100

ns

VDD = 15V

40

80

ns

Maximum Clock

VDD = 5V

2.5

3.5

MHz

Input Frequency

VDD = 10V

5

10

MHz

VDD = 15V

8

Minimum Clock

VDD = 5V

100

200

Pulse Width

VDD = 10V

50

100

ns

VDD = 15V

40

80

ns

16

VDD = 5V

15

µs

VDD = 10V

15

µs

VDD = 15V

15

µs

Minimum Set-Up Time Serial Input

VDD = 5V

60

120

ns

tH ≥ 200 ns

VDD = 10V

40

80

ns

(Ref. to CL)

VDD = 15V

30

60

ns

Parallel Inputs

VDD = 5V

25

50

ns

tH ≥ 200 ns

VDD = 10V

15

30

ns

VDD = 15V

10

20

ns

Minimum Hold Time Parallel/Serial Control

tREM

ns

Clock Rise and

VDD = 5V

Serial In, Parallel In, ts ≥ 400 ns VDD = 10V tWH

MHz

Fall Time (Note 6)

(Ref. to P/S) tH

Typ

VDD = 5V

VDD = 15V

0

ns

10

ns

15

ns

Minimum P/S

VDD = 5V

150

250

ns

Pulse Width

VDD = 10V

75

125

ns

VDD = 15V

50

100

ns

VDD = 5V

100

200

ns

VDD = 10V

50

100

ns

VDD = 15V

40

80

ns

5

7.5

Minimum P/S Removal Time (Ref. to CL)

CI

Average Input Capacitance

D

Power Dissipation

Any Input

100

pF pF

Capacitance (Note 8) Note 6: AC Parameters are guaranteed by DC correlated testing. Note 7: If more than one unit is cascaded trCL should be made less than or equal to the fixed propagation delay of the output of the driving stage for the estimated capacitive load. Note 8: D determines the no load AC power consumption of any CMOS device. For complete explanation, see 74C family characteristics application note AN-90.


4

CD4021BC


5


CD4021BC

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body Package Number M16A


6

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E

LIFE POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life 1. Life devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life body, or (b) or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com .

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

CD4021BC 8-Stage Static Shift

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)


CD4023BM/CD4023BC Buffered Triple 3-Input NAND Gate CD4025BM/CD4025BC Buffered Triple 3-Input NOR Gate General Description

Features

These triple gates are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. They have equal source and sink current capabilities and conform to standard B series output drive. The devices also have buffered outputs which improve transfer characteristics by providing very high gain. All inputs are protected against static discharge with diodes to VDD and VSS.

Y Y Y

Y Y Y

Wide supply voltage range 3.0V to 15V High noise immunity 0.45 VDD (typ.) Low power TTL fan out of 2 driving 74L compatibility or 1 driving 74LS 5V – 10V – 15V parametric ratings Symmetrical output characteristics Maximum input leakage 1 mA at 15V over full temperature range

Connection Diagrams CD4025BM/CD4025BC Dual-In-Line Package

CD4023BM/CD4023BC Dual-In-Line Package

TL/F/5956 – 1

Top View

TL/F/5956 – 2

Top View Order Number CD4023B or CD4025B


TL/F/5956


CD4023BM/CD4023BC Buffered Triple 3-Input NAND Gate CD4025BM/CD4025BC Buffered Triple 3-Input NOR Gate

February 1988

Absolute Maximum Ratings (Notes 1 & 2)

Recommended Operating Conditions

If Military/Aerospace specified devices are required, please the National Semiconductor Sales Office/Distributors for availability and specifications. DC Supply Voltage (VDD) Input Voltage (VIN) Storage Temp. Range (TS) Power Dissipation (PD) Dual-In-Line Small Outline Lead Temperature (TL) (Soldering, 10 seconds)

DC Supply Voltage (VDD) Input Voltage (VIN) Operating Temperature Range (TA) CD4023BM, CD4025BM CD4023BC, CD4025BC

b 0.5 VDC to a 18 VDC b 0.5 VDC to VDD a 0.5 VDC b 65§ C to a 150§ C

5 VDC to 15 VDC 0 VDC to VDD VDC b 55§ C to a 125§ C b 40§ C to a 85§ C

700 mW 500 mW 260§ C

DC Electrical Characteristics CD4023BM, CD4025BM (Note 2) Symbol

Parameter

b 55§ C

Conditions

Min

Typ

a 25§ C

Min

a 125§ C

Typ

Max

Min

Units

Max

IDD

Quiescent Device Current VDD e 5V VDD e 10V VDD e 15V

0.25 0.5 1.0

0.004 0.005 0.006

0.25 0.5 1.0

7.5 15 30

mA mA mA

VOL

Low Level Output Voltage VDD e 5V VDD e 10V VDD e 15V

0.05 0.05 0.05

0 0 0

0.05 0.05 0.05

0.05 0.05 0.05

V V V

VOH

High Level Output Voltage VDD e 5V VDD e 10V VDD e 15V

VIL


VIH


IOL

Low Level Output Current VDD e 5V, VO e 0.4V (Note 3) VDD e 10V, VO e 0.5V VDD e 15V, VO e 1.5V

IOH

High Level Output Current VDD e 5V, VO e 4.6V (Note 3) VDD e 10V, VO e 9.5V VDD e 15V, VO e 13.5V

IIN

Input Current

4.95 9.95 14.95

VDD e 5V, VO e 4.5V VDD e 10V, VO e 9.0V VDD e 15V, VO e 13.5V

lIOl k1mA


IOl k1mA

( (l

4.95 9.95 14.95 1.5 3.0 4.0

5 10 15 2 4 6

4.95 9.95 14.95

V V V

1.5 3.0 4.0

1.5 3.0 4.0

3.5 7.0 11.0

3.5 7.0 11.0

3 6 9

3.5 7.0 11.0

V V V

0.64 1.6 4.2

0.51 1.3 3.4

0.88 2.2 8

0.36 0.90 2.4

mA mA mA

b 0.36 b 0.90 b 2.4

mA mA mA

b 0.64 b 1.6 b 4.2

VDD e 15V, VIN e 0V VDD e 15V, VIN e 15V

b 0.51 b 0.88 b 1.3 b 2.2 b 3.4 b8 b 0.10

0.10

b 10 b 5 b 0.10

10b5

b 1.0

0.10

Schematic Diagram CD4023BC/CD4023BM

(/3 Device Shown *All Inputs Protected by Standard CMOS Input Protection Circuit.

TL/F/5956 – 3

2

V V V

1.0

mA mA

DC Electrical Characteristics CD4023BC, CD4025BC (Note 2) Symbol

Parameter

b 40§ C

Conditions

Min

Typ

a 25§ C

Min

a 85§ C

Typ

Max

Min

Units

Max

IDD


1.0 2.0 4.0

0.004 0.005 0.006

1.0 2.0 4.0

7.5 15 30

mA mA mA

VOL

Low Level Output Voltage VDD e 5V VDD e 10V VDD e 15V

0.05 0.05 0.05

0 0 0

0.05 0.05 0.05

0.05 0.05 0.05

V V V

VOH

High Level Output Voltage VDD e 5V VDD e 10V VDD e 15V

VIL


VIH


4.95 9.95 14.95


lIOl k1mA


IO k1mA

( (ll

IOL

Low Level Output Current VDD e 5V, VO e 0.4V (Note 3) VDD e 10V, VO e 0.5V VDD e 15V, VO e 1.5V

IOH

High Level Output Current VDD e 5V, VO e 4.6V (Note 3) VDD e 10V, VO e 9.5V VDD e 15V, VO e 13.5V

IIN

Input Current

4.95 9.95 14.95 1.5 3.0 4.0

5 10 15

4.95 9.95 14.95

2 4 6

1.5 3.0 4.0

V V V 1.5 3.0 4.0

V V V

3.5 7.0 11.0

3.5 7.0 11.0

3 6 9

3.5 7.0 11.0

V V V

0.52 1.3 3.6

0.44 1.1 3.0

0.88 2.2 8

0.36 0.90 2.4

mA mA mA

b 0.36 b 0.90 b 2.4

mA mA mA

b 0.52 b 1.3 b 3.6


b 0.44 b 0.88 b 1.1 b 2.2 b 3.0 b8 b 0.3

0.3

b 10 b 5 b 0.3

10b5

0.3

b 1.0

1.0

mA mA

Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provides conditions for actual device operation. Note 2: VSS e 0V unless otherwise specified. Note 3: IOH and IOL are tested one output at a time.

Schematic Diagram CD4025BM/CD4025BC

(/3 Device Shown *All Inputs Protected by Standard CMOS Input Protection Circuit.

TL/F/5956 – 4

3

AC Electrical Characteristics* TA e 25§ C, CL e 50 pF, RL e 200k, unless otherwise specified Symbol

Parameter

CD4023BC CD4023BM

Conditions Min

CD4025BC CD4025BM

Typ

Max

Min

Units

Typ

Max

tPHL

Propagation Delay, High-to-Low Level

VDD e 5V VDD e 10V VDD e 15V

130 60 40

250 100 70

130 60 40

250 100 70

ns ns ns

tPLH

Propagation Delay, Low-to-High Level


110 50 35

250 100 70

120 60 40

250 100 70

ns ns ns

tTHL, tTLH

Transition Time


90 50 40

200 100 80

90 50 40

200 100 80

ns ns ns

CIN


Any Input

5

7.5

5

7.5

pF

D

Power Dissipation Capacity (Note 4)

Any Gate

17

17

pF

*AC Parameters are guaranteed by DC correlated testing. Note 4: D determines the no load AC power consumption of any CMOS device. For complete explanation, see 54C/74C Family Characteristics Application Note AN-90.

4


Ceramic Dual-In-Line Package (J) Order Number CD4023BMJ, CD4023BCJ, CD4025BMJ or CD4025BCJ NS Package Number J14A

5

CD4023BM/CD4023BC Buffered Triple 3-Input NAND Gate CD4025BM/CD4025BC Buffered Triple 3-Input NOR Gate


Molded Dual-In-Line Package (N) Order Number CD4023BMN, CD4023BCN, CD4025BMN or CD4025BCN NS Package Number N14A
























CD4029BM/CD4029BC Presettable Binary/Decade Up/Down Counter General Description The CD4029BM/CD4029BC is a presettable up/down counter which counts in either binary or decade mode depending on the voltage level applied at binary/decade input. When binary/decade is at logical ‘‘1’’, the counter counts in binary, otherwise it counts in decade. Similarly, the counter counts up when the up/down input is at logical ‘‘1’’ and vice versa. A logical ‘‘1’’ preset enable signal allows information at the ‘‘jam’’ inputs to preset the counter to any state asynchronously with the clock. The counter is advanced one count at the positive-going edge of the clock if the carry in and preset enable inputs are at logical ‘‘0’’. Advancement is inhibited when either or both of these two inputs is at logical ‘‘1’’. The carry out signal is normally at logical ‘‘1’’ state and goes to logical ‘‘0’’ state when the counter reaches its maximum

count in the ‘‘up’’ mode or the minimum count in the ‘‘down’’ mode provided the carry input is at logical ‘‘0’’ state. All inputs are protected against static discharge by diode clamps to both VDD and VSS.

Features Y Y Y

Y Y

Wide supply voltage range High noise immunity Low power TTL compatibility

3V to 15V 0.45 VDD (typ.) fan out of 2 driving 74L or 1 driving 74LS

Parallel jam inputs Binary or BCD decade up/down counting

Logic Diagram

TL/F/5960 – 1


TL/F/5960


CD4029BM/CD4029BC Presettable Binary/Decade Up/Down Counter

February 1988

Absolute Maximum Ratings


(Notes 1 and 2) If Military/Aerospace specified devices are required, please the National Semiconductor Sales Office/Distributors for availability and specifications. b 0.5V to a 18 VDC DC Supply Voltage (VDD)

DC Supply Voltage (VDD) Input Voltage (VIN) Operating Temperature Range (TA) CD4029BM CD4029BC

b 0.5V to VDD a 0.5 VDC Input Voltage (VIN) b 65§ C to a 150§ C Storage Temperature Range (TS) Power Dissipation (PD) Dual-In-Line 700 mW Small Outline 500 mW Lead Temperature (TL) (Soldering, 10 seconds) 260§ C

3V to 15 VDC 0V to VDD VDC b 55§ C to a 125§ C b 40§ C to a 85§ C

DC Electrical Characteristics CD4029BM (Note 2) Symbol

Parameter

b 55§ C

Conditions

Min

Max

a 25§ C

Min

IDD


VOL

Low Level Output Voltage

lIOl k 1 mA VDD e 5V VDD e 10V VDD e 15V

High Level Output Voltage


VIL


VDD e 5V, VO e 0.5V or 4.5V VDD e 10V, VO e 1V or 9V VDD e 15V, VO e 1.5V or 13.5V

VIH



3.5 7.0 11.0

3.5 7.0 11.0

IOL

Low Level Output Current (Note 3)


0.64 1.6 4.2

0.51 1.3 3.4

IOH

High Level Output Current (Note 3)


b 0.64 b 1.6 b 4.2

b 0.51 b 1.3 b 3.4

IIN

Input Current


VOH

Typ

5 10 20 0.05 0.05 0.05 4.95 9.95 14.95

0 0 0 4.95 9.95 14.95

a 125§ C

Min

Max

5 10 20

5

150 300 600

mA mA mA

0.05 0.05 0.05

V V V

0.05 0.05 0.05

5 10 15

1.5 3.0 4.0

4.95 9.95 14.95

V V V

1.5 3.0 4.0

1.5 3.0 4.0

V V V

0.88 2.25 8.8

0.36 0.9 2.4

mA mA mA

b 0.88 b 2.25 b 8.8

b 0.36 b 0.9 b 2.4

mA mA mA

10b5

0.1

V V V

3.5 7.0 11.0

b 10 b 5 b 0.1

b 0.1

Units

Max

b 1.0

0.1

1.0

mA mA

DC Electrical Characteristics CD4029BC (Note 2) Symbol

Parameter

Conditions

b 40§ C

Min

a 25§ C

Max

IDD



20 40 80

VOL



0.05 0.05 0.05



VOH

4.95 9.95 14.95

Min

Typ

0 0 0 4.95 9.95 14.95

5 10 15

a 85§ C

Max

Min

Units

Max

20 40 80

150 300 600

mA mA mA

0.05 0.05 0.05

0.05 0.05 0.05

V V V

4.95 9.95 14.95

V V V

Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation. Note 2: VSS e 0V unless otherwise specified. Note 3: IOH and IOL are tested one output at a time.

2

DC Electrical Characteristics CD4029BC (Note 2) (Continued) Symbol

Parameter

b 40§ C

Conditions

Min

Max

a 25§ C

Min

Typ

VIL



1.5 3.0 4.0

VIH



3.5 7.0 11.0

3.5 7.0 11.0

IOL



0.52 1.3 3.6

0.44 1.1 3.0

IOH



b 0.52 b 1.3 b 3.6

b 0.44 b 1.1 b 3.0

IIN

Input Current


a 85§ C

Max

Min

1.5 3.0 4.0

Units

Max 1.5 3.0 4.0

V V V

3.5 7.0 11.0

V V V

0.88 2.25 8.8

0.36 0.9 2.4

mA mA mA

b 0.88 b 2.25 b 8.8

b 0.36 b 0.9 b 2.4

mA mA mA

b 0.3

b 10 b 5

b 0.3

b 1.0

0.3

10b5

0.3

1.0

mA mA

AC Electrical Characteristics* TA e 25§ C, CL e 50 pF, RL e 200k, Input trCL e tfCL e 20 ns, unless otherwise specified Symbol

Parameter

Conditions

Min

Typ

Max

Units

CLOCKED OPERATION tPHL or tPLH

Propagation Delay Time to Q Outputs


200 85 70

400 170 140

ns ns ns

tPHL or tPLH

Propagation Delay Time to Carry Output


320 135 110

640 270 220

ns ns ns

tPHL or tPLH


CL e 15 pF VDD e 5V VDD e 10V VDD e 15V

285 120 95

570 240 190

ns ns ns

tTHL or tTLH

Transition Time/Q or Carry Output


100 50 40

200 100 80

ns ns ns

tWH or tWL

Minimum Clock Pulse Width


160 70 55

320 135 110

ns ns ns

trCL or tfCL

Maximum Clock Rise and Fall Time


tSU

Minimum Set-Up Time


fCL

Maximum Clock Frequency


CIN


Any Input

5

D

Power Dissipation Capacitance

Per Package (Note 4)

65

15 10 5

ms ms ms 180 70 55

1.5 3.7 4.5

360 140 110

3.1 7.4 9

ns ns ns MHz MHz MHz

7.5

pF pF

Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation. Note 2: VSS e 0V unless otherwise specified. Note 3: IOH and IOL are tested one output at a time.

3

AC Electrical Characteristics* TA e 25§ C, CL e 50 pF, RL e 200 k, Input trCL e tfCL e 20 ns, unless otherwise specified (Continued) Symbol

Parameter

Conditions

Min

Typ

Max

Units

PRESET ENABLE OPERATION tPHL or tPLH

Propagation Delay Time to Q output


285 115 95

570 230 195

ns ns ns

tPHL or tPLH



400 165 135

800 330 260

ns ns ns

tWH

Minimum Preset Enable Pulse Width


80 30 25

160 60 50

ns ns ns

tREM

Minimum Preset Enable Removal Time


150 60 50

300 120 100

ns ns ns

CARRY INPUT OPERATION tPHL or tPLH



265 110 90

530 220 180

ns ns ns

tPHL, tPLH


CL e 15 pF VDD e 5V VDD e 10V VDD e 15V

200 85 70

400 170 140

ns ns ns

*AC Parameters are guaranteed by DC correlated testing. Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation. Note 2: VSS e 0V unless otherwise specified. Note 3: IOH and IOL are tested one output at a time. Note 4: D determines the no load AC power consumption of any CMOS device. For complete explanation, see 54C/74C Family Characteristics application note, AN-90.

Connection Diagram Dual-In-Line Package

Order Number CD4029B

TL/F/5960–2

Top View

4

Logic Waveforms Decade Mode

TL/F/5960 – 3

Binary Mode

TL/F/5960 – 4

5

Switching Time Waveforms

TL/F/5960 – 5

Cascading Packages Parallel Clocking

TL/F/5960 – 6

Ripple Clocking

TL/F/5960 – 7

Carry out lines at the 2nd or later stages may have a negative-going spike due to differential internal delays. These spikes do not affect counter operation, but if the carry out is used to trigger external circuitry the carry out should be gated with the clock.

6

7

CD4029BM/CD4029BC Presettable Binary/Decade Up/Down Counter


Order Number CD4029BMJ or CD4029BCJ NS Package Number J16A

Order Number CD4029BMN or CD4029BCN NS Package Number N16E

















CD4020BC • CD4040BC • CD4060BC 14-Stage Ripple Carry Binary Counters • 12-Stage Ripple Carry Binary Counters • 14-Stage Ripple Carry Binary Counters General Description

Features

The CD4020BC, CD4060BC are 14-stage ripple carry binary counters, and the CD4040BC is a 12-stage ripple carry binary counter. The counters are advanced one count on the negative transition of each clock pulse. The counters are reset to the zero state by a logical “1” at the reset input independent of clock.

■ Wide supply voltage range: ■ High noise immunity:

1.0V to 15V

0.45 VDD (typ.)

■ Low power TTL compatibility: Fan out of 2 driving 74L or 1 driving 74LS ■ Medium speed operation: 8 MHz typ. at VDD = 10V ■ Schmitt trigger clock input

Ordering Code: Order Number CD4020BCM

Package Number M16A

Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow

CD4020BCN

N16E


CD4040BCM

M16A

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow

CD4040BCSJ

M16D

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

CD4040BCN

N16E


CD4060BCM

M16A


CD4060BCN

N16E



Connection Diagrams Pin Assignments for DIP and SOIC CD4020BC

Pin Assignments for DIP, SOIC and SOP CD4040BC

Top View

Top View


DS005953.prf


CD4020BC • CD4040BC • CD4060BC 14-Stage Ripple Carry Binary Counters • 12-Stage Ripple Carry Binary Counters • 14-Stage Ripple Carry Binary Counters

October 1987

CD4020BC • CD4040BC • CD4060BC

Connection Diagrams

(Continued) Pin Assignments for DIP and SOIC CD4060BC

Top View

Schematic Diagrams CD4020BC

CD4040BC


2


CD4060BC

CD4060B Typical Oscillator Connections RC Oscillator

Crystal Oscillator

3



Absolute Maximum Ratings(Note 1)


(Note 2) Supply Voltage (VDD) Input Voltage (VIN) Storage Temperature Range (TS)

−0.5V to +18V

Input Voltage (VIN)

−65°C to +150°C 700 mW

Small Outline

500 mW

−40°C to +85°C

Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The tables of “Recommended Operating Conditions” and “Electrical Characteristics” provide conditions for actual device operation.


0V to VDD


Package Dissipation (PD) Dual-In-Line

+3V to +15V


−0.5V to VDD +0.5V


260°C

DC Electrical Characteristics (Note 2) Symbol IDD

VOL

Parameter Quiescent Device Current

LOW Level Output Voltage

−40°C

Conditions

Min

VIL

VIH

IOL

HIGH Level Output Voltage


HIGH Level Input Voltage

LOW Level Output Current

IIN

Typ

+85°C Max

Min

Max

Units


20

20

150

µA

40

40

300

µA


80

80

600

µA

VDD = 5V

0.05

0

0.05

0.05

V

VDD = 10V

0.05

0

0.05

0.05

V

0

0.05

0.05

VDD = 5V

4.95

4.95

5

0.05 4.95

V V

VDD = 10V

9.95

9.95

10

9.95

V

VDD = 15V

14.95

14.95

15

14.95

V

VDD = 5V, VO = 0.5V or 4.5V

1.5

2

1.5

1.5

VDD = 10V, VO = 1.0V or 9.0V

3.0

4

3.0

3.0

V

VDD = 15V, VO = 1.5V or 13.5V

4.0

6

4.0

4.0

V

V

VDD = 5V, VO = 0.5V or 4.5V

3.5

3.5

3

3.5

V

VDD = 10V, VO = 1.0V or 9.0V

7.0

7.0

6

7.0

V

VDD = 15V, VO = 1.5V or 13.5V

11.0

11.0

9

11.0

V

VDD = 5V, VO = 0.4V

0.52

0.44

0.88

0.36

mA

VDD = 10V, VO = 0.5V

1.3

1.1

2.25

0.9

mA

VDD = 15V, VO = 1.5V

3.6

3.0

8.8

2.4

mA

HIGH Level Output Current

VDD = 5V, VO = 4.6V

−0.52

−0.44

−0.88

−0.36

mA

(Note 3)

VDD = 10V, VO = 9.5V

−1.3

−1.1

−2.25

−0.9

mA

VDD = 15V, VO = 13.5V

−3.6

Input Current

VDD = 15V, VIN = 0V

−0.30

−10−5

−0.30

−1.0

µA


0.30

10−5

0.30

1.0

µA

(Note 3) IOH

+25°C Min


VDD = 15V VOH

Max

−3.0

−8.8

Note 3: Data does not apply to oscillator points φ0 and φ0 of CD4060BC. IOH and IOL are tested one output at a time.


4

−2.4

mA

(Note 4)

CD4020BC, CD4040BC TA = 25°C, CL = 50 pF, RL = 200k, tr = tf = 20 ns, unless otherwise noted Symbol tPHL1, tPLH1

tPHL, tPLH

tTHL, tTLH

tWL, tWH

trCL, tfCL

fCL

tPHL(R)

tWH(R)

Parameter

Typ

Max

Units

VDD = 5V

250

550

ns

VDD = 10V

100

210

ns

VDD = 15V

75

150

ns

Interstage Propagation Delay Time

VDD = 5V

150

330

ns

from Qn to Qn+1

VDD = 10V

60

125

ns

VDD = 15V

45

90

ns

VDD = 5V

100

200

ns

VDD = 10V

50

100

ns

VDD = 15V

40

80

ns

VDD = 5V

125

335

ns

VDD = 10V

50

125

ns

VDD = 15V

40

100

ns

VDD = 5V

No Limit

ns

VDD = 10V

No Limit

ns

VDD = 15V

No Limit

Propagation Delay Time to Q1

Transition Time




Reset Propagation Delay

Minimum Reset Pulse Width

CIN


D


Conditions

Min

ns

VDD = 5V

1.5

4

MHz

VDD = 10V

4

10

MHz

VDD = 15V

5

12

MHz

VDD = 5V

200

450

ns

VDD = 10V

100

210

ns

VDD = 15V

80

170

ns

VDD = 5V

200

450

ns

VDD = 10V

100

210

ns

VDD = 15V

80

170

ns

Any Input

5

7.5

pF

50

pF

Note 4: AC Parameters are guaranteed by DC correlated testing.

5






(Note 5)

CD4060BC TA = 25°C, CL = 50 pF, RL = 200k, tr = tf = 20 ns, unless otherwise noted Symbol tPHL4, tPLH4

tPHL, tPLH

tTHL, tTLH

tWL, tWH

trCL, tfCL

fCL

tPHL(R)

tWH(R)

Parameter

Typ

Max

Units

VDD = 5V

550

1300

ns

VDD = 10V

250

525

ns

VDD = 15V

200

400

ns


VDD = 5V

150

330

ns

from Qn to Qn+1

VDD = 10V

60

125

ns

VDD = 15V

45

90

ns

VDD = 5V

100

200

ns

VDD = 10V

50

100

ns

VDD = 15V

40

80

ns

VDD = 5V

170

500

ns

VDD = 10V

65

170

ns

VDD = 15V

50

125

ns

VDD = 5V

No Limit

ns

VDD = 10V

No Limit

ns

VDD = 15V

No Limit


Transition Time






CIN


D


Conditions

VDD = 5V

1

3

ns MHz

VDD = 10V

3

8

MHz

VDD = 15V

4

10

MHz

VDD = 5V

200

450

ns

VDD = 10V

100

210

ns

VDD = 15V

80

170

ns

VDD = 5V

200

450

ns

VDD = 10V

100

210

ns

VDD = 15V

80

170

ns

Any Input

5

7.5

pF

50



Min

6

pF



16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Package Number M16A

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D

7









CD4020BC • CD4040BC • CD4060BC 14-Stage Ripple Carry Binary Counters • 12-Stage Ripple Carry Binary Counters • 14-Stage Ripple Carry Binary Counters General Description

Features

The CD4020BC, CD4060BC are 14-stage ripple carry binary counters, and the CD4040BC is a 12-stage ripple carry binary counter. The counters are advanced one count on the negative transition of each clock pulse. The counters are reset to the zero state by a logical “1” at the reset input independent of clock.

■ Wide supply voltage range: ■ High noise immunity:

1.0V to 15V

0.45 VDD (typ.)

■ Low power TTL compatibility: Fan out of 2 driving 74L or 1 driving 74LS ■ Medium speed operation: 8 MHz typ. at VDD = 10V ■ Schmitt trigger clock input


Package Number M16A

Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow

CD4020BCN

N16E


CD4040BCM

M16A


CD4040BCSJ

M16D


CD4040BCN

N16E


CD4060BCM

M16A


CD4060BCN

N16E



Connection Diagrams Pin Assignments for DIP and SOIC CD4020BC

Pin Assignments for DIP, SOIC and SOP CD4040BC

Top View

Top View


DS005953.prf



October 1987


Connection Diagrams

(Continued) Pin Assignments for DIP and SOIC CD4060BC

Top View

Schematic Diagrams CD4020BC

CD4040BC


2


CD4060BC

CD4060B Typical Oscillator Connections RC Oscillator

Crystal Oscillator

3



Absolute Maximum Ratings(Note 1)


(Note 2) Supply Voltage (VDD) Input Voltage (VIN) Storage Temperature Range (TS)

−0.5V to +18V

Input Voltage (VIN)

−65°C to +150°C 700 mW

Small Outline

500 mW

−40°C to +85°C

Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The tables of “Recommended Operating Conditions” and “Electrical Characteristics” provide conditions for actual device operation.


0V to VDD


Package Dissipation (PD) Dual-In-Line

+3V to +15V


−0.5V to VDD +0.5V


260°C

DC Electrical Characteristics (Note 2) Symbol IDD

VOL

Parameter Quiescent Device Current

LOW Level Output Voltage

−40°C

Conditions

Min

VIL

VIH

IOL

HIGH Level Output Voltage


HIGH Level Input Voltage

LOW Level Output Current

IIN

Typ

+85°C Max

Min

Max

Units


20

20

150

µA

40

40

300

µA


80

80

600

µA

VDD = 5V

0.05

0

0.05

0.05

V

VDD = 10V

0.05

0

0.05

0.05

V

0

0.05

0.05

VDD = 5V

4.95

4.95

5

0.05 4.95

V V

VDD = 10V

9.95

9.95

10

9.95

V

VDD = 15V

14.95

14.95

15

14.95

V

VDD = 5V, VO = 0.5V or 4.5V

1.5

2

1.5

1.5

VDD = 10V, VO = 1.0V or 9.0V

3.0

4

3.0

3.0

V

VDD = 15V, VO = 1.5V or 13.5V

4.0

6

4.0

4.0

V

V

VDD = 5V, VO = 0.5V or 4.5V

3.5

3.5

3

3.5

V

VDD = 10V, VO = 1.0V or 9.0V

7.0

7.0

6

7.0

V

VDD = 15V, VO = 1.5V or 13.5V

11.0

11.0

9

11.0

V

VDD = 5V, VO = 0.4V

0.52

0.44

0.88

0.36

mA

VDD = 10V, VO = 0.5V

1.3

1.1

2.25

0.9

mA

VDD = 15V, VO = 1.5V

3.6

3.0

8.8

2.4

mA

HIGH Level Output Current

VDD = 5V, VO = 4.6V

−0.52

−0.44

−0.88

−0.36

mA

(Note 3)

VDD = 10V, VO = 9.5V

−1.3

−1.1

−2.25

−0.9

mA

VDD = 15V, VO = 13.5V

−3.6

Input Current

VDD = 15V, VIN = 0V

−0.30

−10−5

−0.30

−1.0

µA


0.30

10−5

0.30

1.0

µA

(Note 3) IOH

+25°C Min


VDD = 15V VOH

Max

−3.0

−8.8

Note 3: Data does not apply to oscillator points φ0 and φ0 of CD4060BC. IOH and IOL are tested one output at a time.


4

−2.4

mA

(Note 4)

CD4020BC, CD4040BC TA = 25°C, CL = 50 pF, RL = 200k, tr = tf = 20 ns, unless otherwise noted Symbol tPHL1, tPLH1

tPHL, tPLH

tTHL, tTLH

tWL, tWH

trCL, tfCL

fCL

tPHL(R)

tWH(R)

Parameter

Typ

Max

Units

VDD = 5V

250

550

ns

VDD = 10V

100

210

ns

VDD = 15V

75

150

ns


VDD = 5V

150

330

ns

from Qn to Qn+1

VDD = 10V

60

125

ns

VDD = 15V

45

90

ns

VDD = 5V

100

200

ns

VDD = 10V

50

100

ns

VDD = 15V

40

80

ns

VDD = 5V

125

335

ns

VDD = 10V

50

125

ns

VDD = 15V

40

100

ns

VDD = 5V

No Limit

ns

VDD = 10V

No Limit

ns

VDD = 15V

No Limit


Transition Time






CIN


D


Conditions

Min

ns

VDD = 5V

1.5

4

MHz

VDD = 10V

4

10

MHz

VDD = 15V

5

12

MHz

VDD = 5V

200

450

ns

VDD = 10V

100

210

ns

VDD = 15V

80

170

ns

VDD = 5V

200

450

ns

VDD = 10V

100

210

ns

VDD = 15V

80

170

ns

Any Input

5

7.5

pF

50

pF


5






(Note 5)

CD4060BC TA = 25°C, CL = 50 pF, RL = 200k, tr = tf = 20 ns, unless otherwise noted Symbol tPHL4, tPLH4

tPHL, tPLH

tTHL, tTLH

tWL, tWH

trCL, tfCL

fCL

tPHL(R)

tWH(R)

Parameter

Typ

Max

Units

VDD = 5V

550

1300

ns

VDD = 10V

250

525

ns

VDD = 15V

200

400

ns


VDD = 5V

150

330

ns

from Qn to Qn+1

VDD = 10V

60

125

ns

VDD = 15V

45

90

ns

VDD = 5V

100

200

ns

VDD = 10V

50

100

ns

VDD = 15V

40

80

ns

VDD = 5V

170

500

ns

VDD = 10V

65

170

ns

VDD = 15V

50

125

ns

VDD = 5V

No Limit

ns

VDD = 10V

No Limit

ns

VDD = 15V

No Limit


Transition Time






CIN


D


Conditions

VDD = 5V

1

3

ns MHz

VDD = 10V

3

8

MHz

VDD = 15V

4

10

MHz

VDD = 5V

200

450

ns

VDD = 10V

100

210

ns

VDD = 15V

80

170

ns

VDD = 5V

200

450

ns

VDD = 10V

100

210

ns

VDD = 15V

80

170

ns

Any Input

5

7.5

pF

50



Min

6

pF



16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Package Number M16A


7









CD4043BC • CD4044BC Quad 3-STATE NOR R/S Latches • Quad 3-STATE NAND R/S Latches General Description

Features

The CD4043BC are quad cross-couple 3-STATE CMOS NOR latches, and the CD4044BC are quad cross-couple 3STATE CMOS NAND latches. Each latch has a separate Q output and individual SET and RESET inputs. There is a common 3-STATE ENABLE input for all four latches. A logic “1” on the ENABLE input connects the latch states to the Q outputs. A logic “0” on the ENABLE input disconnects the latch states from the Q outputs resulting in an open circuit condition on the Q output. The 3-STATE feature allows common bussing of the outputs.

■ Wide supply voltage range:

3V to 15V

■ Low power: 100 nW (typ.) ■ High noise immunity:

0.45 VDD (typ.)

■ Separate SET and RESET inputs for each latch ■ NOR and NAND configuration ■ 3-STATE output with common output enable

Applications • Multiple bus storage • Strobed • Four bits of independent storage with output enable • General digital logic


Package Number

Package Description

M16A


CD4043BCN

N16E


CD4044BCM

M16A


CD4044BCSJ

M16D


CD4044BCN

N16E



Connection Diagrams Pin Assignments for DIP, SOIC and SOP CD4043BC

Pin Assignments for DIP and SOIC CD4044BC

Top View

Top View


DS005967.prf


CD4043BC • CD4044BC Quad 3-STATE NOR R/S Latches • Quad 3-STATE NAND R/S Latches

October 1987

CD4043BC • CD4044BC

Block Diagrams CD4043BC

CD4044BC

Truth Tables CD4044BC

CD4043BC S

R

E

Q

S

R

E

Q

X

X

0

OC

X

X

0

OC

0

0

1

NC

1

1

1

NC

1

0

1

1

0

1

1

1

0

1

1

0

1

0

1

0

1

1

1

∆

0

0

1

∆∆

OC = 3-STATE NC = No change X = Don’t care ∆ = Dominated by S = 1 input ∆∆ = Dominated by R = 0 input


2


−0.5V to +18V


(Note 2)

−0.5V to VDD +0.5V

Input Voltage (VIN) Storage Temperature Range (TS)


−65°C to +150°C

3.0V to 15V

Input Voltage (VIN)

Power Dissipation (PD)

0 to VDD V


Dual-In-Line

700 mW

Small Outline

500 mW


−40°C to +85°C

CD4043BC, CD4044BC

Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices should be operated at these limits. The tables of “Recommended Operating Conditions” and “Electrical Characteristics” provide conditions for actual device operation.

260°C


DC Electrical Characteristics Symbol IDD

VOL

VOH

VIL

VIH

IOL

IOH

IIN

Parameter

(Note 2) −40°C

Conditions

Min

+25°C

Max

Min

+85°C

Typ

Max

Min

Max

Units

Quiescent


20

0.01

20

150

µA

Device Current


40

0.01

40

300

µA


80

0.02

80

600

µA

LOW Level

|IO| ≤ 1 µA, VIL = 0V, VIH = VDD

Output Voltage

VDD = 5.0V

0.05

0

0.05

0.05

V

VDD = 10V

0.05

0

0.05

0.05

V

VDD = 15V

0.05

0

0.05

0.05

V

HIGH Level

|IO| ≤ 1 µA, VIL = 0V, VIH = VDD

Output Voltage

VDD = 5.0V

4.95

4.95

5.0

4.95

VDD = 10V

9.95

9.95

10

9.95

V

VDD = 15V

14.95

14.95

15

14.95

V

V

LOW Level

|IO| ≤ 1 µA

Input Voltage

VDD = 5.0V, VO = 0.5V or 4.5V

1.5

2.25

1.5

1.5

V

VDD = 10V, VO = 1.0V or 9.0V

3.0

4.5

3.0

3.0

V

VDD = 15V, VO = 1.5V or 13.5V

4.0

6.75

4.0

4.0

V

HIGH Level

|IO| ≤ 1 µA

Input Voltage

VDD = 5.0V, VO = 0.5V or 4.5V

3.5

3.5

3.5

V

VDD = 5.0V, VO = 1.0V or 9.0V

7.0

7.0

7.0

V

VDD = 15V, VO = 1.5V or 13.5V

11

11

11

V

LOW Level

VIL = 0V, VIH = VDD

Output Current

VDD = 5.0V, VO = 0.4V

0.52

0.44

0.88

0.36

mA

(Note 3)

VDD = 10V, VO = 0.5V

1.3

1.1

2.2

0.9

mA

VDD = 15V, VO = 1.5V

3.6

3.0

6.0

2.4

mA

HIGH Level

VIL = 0V, VIH = VDD

Output Current

VDD = 5.0V, VO = 4.6V

−0.52

−0.44

−0.32

−0.36

mA

(Note 3)

VDD = 10V, VO = 9.5V

−1.3

−1.1

−0.8

−0.9

mA

VDD = 15V, VO = 13.5V

−3.6

−3.0

−2.4

−2.4

Input Current

VDD = 15V, VIN = 0V

−0.3

−0.3

−1.0

µA


0.3

0.3

1.0

µA

mA

Note 3: IOH and IOL are tested one output at a time.

3



Absolute Maximum Ratings(Note 1) (Note 2)



(Note 4)

TA = 25°C, CL = 50 pF, RL = 200k, input tr = tf = 20 ns, unless otherwise noted Symbol tPLH, tPHL

tPZH, tPHZ

tPZL, tPLZ

tTHL, tTLH

tWO

Parameter Propagation Delay S or R to Q

Propagation Delay Enable to Q (HIGH)

Propagation Delay Enable to Q (LOW)

Transition Time

Minimum SET or RESET Pulse Width

Typ

Max

Units

VDD = 5.0V

Conditions

175

350

ns

VDD = 10V

75

175

ns

VDD = 15V

60

120

ns

VDD = 5.0V

115

230

ns

VDD = 10V

55

110

ns

VDD = 15V

40

80

ns

VDD = 5.0V

100

200

ns

VDD = 10V

50

100

ns

VDD = 15V

40

80

ns

VDD = 5.0V

100

200

ns

VDD = 10V

50

100

ns

VDD = 15V

40

80

ns

VDD = 5.0V

80

160

ns

VDD = 10V

40

80

ns

VDD = 15V CIN

Input Capacitance

Min

20

40

ns

5.0

7.5

pF


Timing Waveforms CD4043B

CD4044B

Enable Timing


4



16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body Package Number M16A


5


CD4043BC • CD4044BC Quad 3-STATE NOR R/S Latches • Quad 3-STATE NAND R/S Latches


















CD4051B, CD4052B, CD4053B August 1998 - Revised March 2000

Data sheet acquired from Harris Semiconductor SCHS047D

CMOS Analog Multiplexers/Demultiplexers with Logic Level Conversion The CD4051B, CD4052B, and CD4053B analog multiplexers are digitally-controlled analog switches having low ON impedance and very low OFF leakage current. Control of analog signals up to 20VP-P can be achieved by digital signal amplitudes of 4.5V to 20V (if VDD -VSS = 3V, a VDD -VEE of up to 13V can be controlled; for VDD -VEE level differences above 13V, a VDD -VSS of at least 4.5V is required). For example, if VDD = +4.5V, VSS = 0V, and VEE = -13.5V, analog signals from -13.5V to +4.5V can be controlled by digital inputs of 0V to 5V. These multiplexer circuits dissipate extremely low quiescent power over the full VDD -VSS and VDD -VEE supply-voltage ranges, independent of the logic state of the control signals. When a logic “1” is present at the inhibit input terminal, all channels are off.

[ /Title (CD405 1B, CD4052 B, CD4053 B) /Subject (CMOS Analog Multi- The CD4051B is a single 8-Channel multiplexer having three plexbinary control inputs, A, B, and C, and an inhibit input. The ers/Dem three binary signals select 1 of 8 channels to be turned on, ultiplex- and connect one of the 8 inputs to the output. ers with The CD4052B is a differential 4-Channel multiplexer having two binary control inputs, A and B, and an inhibit input. The Logic two binary input signals select 1 of 4 pairs of channels to be Level Conver- turned on and connect the anaputs to the outputs. The CD4053B is a triple 2-Channel multiplexer having three sion) /Author separate digital control inputs, A, B, and C, and an inhibit input. Each control input selects one of a pair of channels () which are connected in a single-pole, double-throw /Keyconfiguration. words (Harris When these devices are used as demultiplexers, the “CHANNEL IN/OUT” terminals are the outputs and the Semi“COMMON OUT/IN” terminals are the inputs. conductor, CD4000 Ordering Information PART NUMBER

TEMP. RANGE (oC)

• Wide Range of Digital and Analog Signal Levels - Digital . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 20V - Analog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤20VP-P • Low ON Resistance, 125Ω (Typ) Over 15VP-P Signal Input Range for VDD -VEE = 18V • High OFF Resistance, Channel Leakage of ±100pA (Typ) at VDD -VEE = 18V • Logic-Level Conversion for Digital Addressing Signals of 3V to 20V (VDD -VSS = 3V to 20V) to Switch Analog Signals to 20VP-P (VDD -VEE = 20V) • Matched Switch Characteristics, rON = 5Ω (Typ) for VDD -VEE = 15V • Very Low Quiescent Power Dissipation Under All DigitalControl Input and Supply Conditions, 0.2µW (Typ) at VDD -VSS = VDD -VEE = 10V • Binary Address Decoding on Chip • 5V, 10V and 15V Parametric Ratings • 10% Tested for Quiescent Current at 20V • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range, 100nA at 18V and 25oC • Break-Before-Make Switching Eliminates Channel Overlap

Applications • Analog and Digital Multiplexing and Demultiplexing • A/D and D/A Conversion • Signal Gating

PACKAGE

CD4051BF, CD4052BF, CD4053BF

-55 to 125

16 Ld CERAMIC DIP

CD4051BE, CD4052BE, CD4053BE

-55 to 125

16 Ld PDIP

CD4051BM, CD4051BNS

-55 to 125

16 Ld SOIC

CD4051BPW, CD4052BPW, CD4053BPW

-55 to 125

16 Ld TSSOP

1

Features

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. Copyright © 2000, Texas Instruments Incorporated

CD4051B, CD4052B, CD4053B Pinouts CD4051B (PDIP, CDIP, SOIC, TSSOP) TOP VIEW 4 1

16 VDD

6 2

15 2

COM OUT/IN 3

14 1

7 4

13 0

CHANNELS IN/OUT

CD4052B (PDIP, CDIP, TSSOP) TOP VIEW 0 1

16 VDD

2 2

15 2

COMMON “Y” OUT/IN 3

14 1

Y CHANNELS IN/OUT

X CHANNELS IN/OUT

CHANNELS IN/OUT CHANNELS IN/OUT

Y CHANNELS IN/OUT

3 4

13 COMMON “X” OUT/IN

5 5

12 3

1 5

12 0

INH 6

11 A

INH 6

11 3

VEE 7

10 B

VEE 7

10 A

VSS 8

9 C

VSS 8

9 B

X CHANNELS IN/OUT

CD4053B (PDIP, CDIP, TSSOP) TOP VIEW

IN/OUT

by 1

16 VDD

bx 2

15 OUT/IN bx OR by

cy 3

14 OUT/IN ax OR ay

OUT/IN CX OR CY 4

13 ay

IN/OUT CX 5

12 ax

INH 6

11 A

VEE 7

10 B

VSS 8

9 C

IN/OUT

Functional Block Diagrams CD4051B CHANNEL IN/OUT

16 VDD

7

6

5

4

3

2

1

0

4

2

5

1

12

15

14

13 TG

TG A

†

11 TG

B

†

10 LOGIC LEVEL CONVERSION

C

†

9

INH

†

6

BINARY TO 1 OF 8 DECODER WITH INHIBIT

TG

3 TG

TG

TG

TG

8 VSS

7 VEE

† All inputs are protected by standard CMOS protection network.

2

COMMON OUT/IN

CD4051B, CD4052B, CD4053B Functional Block Diagrams

(Continued) CD4052B X CHANNELS IN/OUT 3

2

1

0

11

15

14

12

TG 16 VDD

A

†

10

B

†

9

INH

†

6

TG

BINARY TO 1 OF 4 DECODER WITH INHIBIT

LOGIC LEVEL CONVERSION

TG

COMMON X OUT/IN

TG

13

TG TG

3 COMMON Y OUT/IN

TG TG

8 VSS

7

VEE

1

5

2

4

0

1

2

3

Y CHANNELS IN/OUT

CD4053B

LOGIC LEVEL CONVERSION

16 VDD

BINARY TO 1 OF 2 DECODERS WITH INHIBIT

IN/OUT cy

cx

by

bx

ay

ax

3

5

1

2

13

12 TG

COMMON OUT/IN ax OR ay 14

A

†

11

TG

TG

COMMON OUT/IN bx OR by 15

B

C

†

†

10

TG

TG

9

4 TG

INH

†

COMMON OUT/IN cx OR cy

6

VDD

8

VSS

7

VEE

† All inputs are protected by standard CMOS protection network.

3

CD4051B, CD4052B, CD4053B TRUTH TABLES INPUT STATES INHIBIT

C

B

A

“ON” CHANNEL(S)

0

0

0

0

0

0

0

0

1

1

0

0

1

0

2

0

0

1

1

3

0

1

0

0

4

0

1

0

1

5

0

1

1

0

6

0

1

1

1

7

1

X

X

X

None

CD4051B

CD4052B INHIBIT

B

A

0

0

0

0x, 0y

0

0

1

1x, 1y

0

1

0

2x, 2y

0

1

1

3x, 3y

1

X

X

None

CD4053B INHIBIT

A OR B OR C

0

0

ax or bx or cx

0

1

ay or by or cy

1

X

None

X = Don’t Care

4

CD4051B, CD4052B, CD4053B Absolute Maximum Ratings

Thermal Information

Supply Voltage (V+ to V-) Voltages Referenced to VSS Terminal . . . . . . . . . . . -0.5V to 20V DC Input Voltage Range . . . . . . . . . . . . . . . . . . -0.5V to VDD +0.5V DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . ±10mA

Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W) E Package . . . . . . . . . . . . . . . . . . . . . . 67 N/A F Package . . . . . . . . . . . . . . . . . . . . . . 115 45 D Package . . . . . . . . . . . . . . . . . . . . . . 73 N/A NS Package . . . . . . . . . . . . . . . . . . . . . 64 N/A PW Package. . . . . . . . . . . . . . . . . . . . . 108 N/A Maximum Junction Temperature (Ceramic Package) . . . . . . . . .175oC Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .265oC (SOIC - Lead Tips Only)

Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE: 1. The package thermal impedance is calculated in accordance with JESD51. Common Conditions Here: If Whole Table is For the Full Temp. Range, VSUPPLY = ±5V, AV = +1, RL = 100Ω, Unless Otherwise Specified (Note 3)

Electrical Specifications

LIMITS AT INDICATED TEMPERATURES (oC)

CONDITIONS

25 PARAMETER

VIS (V)

VEE (V)

VSS (V)

VDD (V)

-55

-40

85

125

MIN

TYP

MAX

UNITS

SIGNAL INPUTS (VIS) AND OUTPUTS (VOS) -

-

-

5

5

5

150

150

-

0.04

5

µA

-

-

-

10

10

10

300

300

-

0.04

10

µA

-

-

-

15

20

20

600

600

-

0.04

20

µA

-

-

-

20

100

100

3000

3000

-

0.08

100

µA

-

0

0

5

800

850

1200

1300

-

470

1050

Ω

-

0

0

10

310

330

520

550

-

180

400

Ω

-

0

0

15

200

210

300

320

-

125

240

Ω

Change in ON Resistance (Between Any Two Channels), ∆rON

-

0

0

5

-

-

-

-

-

15

-

Ω

-

0

0

10

-

-

-

-

-

10

-

Ω

-

0

0

15

-

-

-

-

-

5

-

Ω

OFF Channel Leakage Current: Any Channel OFF (Max) or ALL Channels OFF (Common OUT/IN) (Max)

-

0

0

18

-

±0.01

±100 (Note 2)

nA

Capacitance:

-

-5

5-

5

Quiescent Device Current, IDD Max

Drain to Source ON Resistance rON Max 0 ≤ VIS ≤ VDD

Input, CIS

±100 (Note 2)

±1000 (Note 2)

-

-

-

-

-

5

-

pF

CD4051

-

-

-

-

-

30

-

pF

CD4052

-

-

-

-

-

18

-

pF

CD4053

-

-

-

-

-

9

-

pF

-

-

-

-

-

0.2

-

pF

5

-

-

-

-

-

30

60

ns

10

-

-

-

-

-

15

30

ns

15

-

-

-

-

-

10

20

ns

Output, COS

Feedthrough CIOS Propagation Delay Time (Signal Input to Output

VDD

5

RL = 200kΩ, CL = 50pF, tr , tf = 20ns

CD4051B, CD4052B, CD4053B Common Conditions Here: If Whole Table is For the Full Temp. Range, VSUPPLY = ±5V, AV = +1, RL = 100Ω, Unless Otherwise Specified (Continued) (Note 3)

Electrical Specifications

LIMITS AT INDICATED TEMPERATURES (oC)

CONDITIONS

25 PARAMETER

VIS (V)

VEE (V)

VSS (V)

VDD (V)

-55

-40

85

125

MIN

TYP

MAX

UNITS

5

1.5

1.5

1.5

1.5

-

-

1.5

V

10

3

3

3

3

-

-

3

V

15

4

4

4

4

-

-

4

V

5

3.5

3.5

3.5

3.5

3.5

-

-

V

10

7

7

7

7

7

-

-

V

15

11

11

11

11

11

-

-

V

±0.1

µA

CONTROL (ADDRESS OR INHIBIT), VC Input Low Voltage, VIL , Max

VIL = VDD through 1kΩ; VIH = VDD through Input High Voltage, VIH , 1kΩ Min

Input Current, IIN (Max)

VEE = VSS , RL = 1kΩ to VSS , IIS < 2µA on All OFF Channels

VIN = 0, 18

18

±0.1

±0.1

±1

±1

-

±10-5

Propagation Delay Time: Address-to-Signal tr , tf = 20ns, OUT (Channels ON or CL = 50pF, OFF) See Figures 10, RL = 10kΩ 11, 14

0

0

5

-

-

-

-

-

450

720

ns

0

0

10

-

-

-

-

-

160

320

ns

0

0

15

-

-

-

-

-

120

240

ns

-5

0

5

-

-

-

-

-

225

450

ns

0

0

5

-

-

-

-

-

400

720

ns

0

0

10

-

-

-

-

-

160

320

ns

0

0

15

-

-

-

-

-

120

240

ns

-10

0

5

-

-

-

-

-

200

400

ns

0

0

5

-

-

-

-

-

200

450

ns

0

0

10

-

-

-

-

-

90

210

ns

0

0

15

-

-

-

-

-

70

160

ns

-10

0

5

-

-

-

-

-

130

300

ns

-

-

-

-

-

5

7.5

pF

Propagation Delay Time: Inhibit-to-Signal OUT tr , tf = 20ns, (Channel Turning ON) CL = 50pF, See Figure 11 RL = 1kΩ

Propagation Delay Time: Inhibit-to-Signal OUT (Channel Turning OFF) See Figure 15

tr , tf = 20ns, CL = 50pF, RL = 10kΩ

Input Capacitance, CIN (Any Address or Inhibit Input) NOTE:

2. Determined by minimum feasible leakage measurement for automatic testing.

Electrical Specifications TEST CONDITIONS PARAMETER

VIS (V)

VDD (V)

RL (kΩ)

Cutoff (-3dB) Frequency Channel ON (Sine Wave Input)

5 (Note 3)

10

1

VOS at Common OUT/IN

VEE = VSS , V OS 20Log ------------ = – 3dB V IS

6

VOS at Any Channel

LIMITS TYP

UNITS

CD4053

30

MHz

CD4052

25

MHz

CD4051

20

MHz

60

MHz

CD4051B, CD4052B, CD4053B Electrical Specifications TEST CONDITIONS

LIMITS

PARAMETER

VIS (V)

VDD (V)

RL (kΩ)

TYP

UNITS

Total Harmonic Distortion, THD

2 (Note 3)

5

10

0.3

%

3 (Note 3)

10

0.2

%

5 (Note 3)

15

0.12

%

VEE = VSS, fIS = 1kHz Sine Wave -40dB Feedthrough Frequency (All Channels OFF)

5 (Note 3)

10

1

VOS at Common OUT/IN

CD4053

8

MHz

CD4052

10

MHz

CD4051

12

MHz

VOS at Any Channel

8

MHz

Between Any 2 Channels

3

MHz

Between Sections, CD4052 Only

Measured on Common

6

MHz

Measured on Any Channel

10

MHz

Between Any Two Sections, CD4053 Only

In Pin 2, Out Pin 14

2.5

MHz

In Pin 15, Out Pin 14

6

MHz

10 (Note 4)

65

mVPEAK

VEE = 0, VSS = 0, tr , tf = 20ns, VCC = VDD - VSS (Square Wave)

65

mVPEAK


-40dB Signal Crosstalk Frequency

%

5 (Note 3)

10

1


Address-or-Inhibit-to-Signal Crosstalk

-

10

NOTES: V DD – V EE ----------------------------2

3. Peak-to-Peak voltage symmetrical about 4. Both ends of channel.

Typical Performance Curves 300 VDD - VEE = 10V

VDD - VEE = 5V

rON , CHANNEL ON RESISTANCE (Ω)


600

500

400 TA = 125oC

300

TA = 25oC

200

TA = -55oC 100

0 -4

-3

-2

-1

0

1

2

3

4

VIS , INPUT SIGNAL VOLTAGE (V)

FIGURE 1. CHANNEL ON RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES)

7

5

250 TA = 125oC

200

150 TA = 25oC 100 TA = -55oC 50

0 -10

-7.5

-5 -2.5 0 2.5 5 VIS , INPUT SIGNAL VOLTAGE (V)

7.5


10

CD4051B, CD4052B, CD4053B Typical Performance Curves

(Continued)

600

250 rON , CHANNEL ON RESISTANCE (Ω)


TA = 25oC VDD - VEE = 5V

500 400 300 200

10V 15V

100 0 -10

-7.5

-5

-2.5

0

2.5

5

7.5

VDD - VEE = 15V 200

TA = 125oC

150 TA = 25oC

100

TA = -55oC 50

0 -10

10

-7.5

-5


PD , POWER DISSIPATION PACKAGE (µW)

100Ω

-2

-4

-2 0 2 4 VIS , INPUT SIGNAL VOLTAGE (V)

TA = 25oC ALTERNATING “O” AND “I” PATTERN CL = 50pF

f

VDD = 15V 103 VDD = 10V 102

VDD = 5V CL = 15pF

10 1

10

TEST CIRCUIT VDD

CD4029 VDD B/D A B 100Ω 10 9 1 3 CL 13 5 12 2 4 CD4052 14 15 6 11 7 8

Ι

102 103 104 SWITCHING FREQUENCY (kHz)

105

FIGURE 7. DYNAMIC POWER DISSIPATION vs SWITCHING FREQUENCY (CD4052B)

8

VDD = 5V

10

B/D CD4029 A B C

VDD 100Ω 11 10 9 13 14 15 12 CD4051 1 5 3 2 48 7 6 C L 100Ω

Ι

CL = 15pF 1

100Ω


VDD = 10V

10

6

FIGURE 5. ON CHARACTERISTICS FOR 1 OF 8 CHANNELS (CD4051B)

104

7.5

f

VDD = 15V

102

-4

10


105



VOS , OUTPUT SIGNAL VOLTAGE (V)

1kΩ 500Ω

103

-6

5

TEST CIRCUIT VDD

TA = 25oC ALTERNATING “O” AND “I” PATTERN CL = 50pF 104

RL = 100kΩ, RL = 10kΩ

0

105

2.5

105

VDD = 5V VSS = 0V VEE = -5V TA = 25oC

2

-6

0


6

4

-2.5



105

TA = 25oC ALTERNATING “O” AND “I” PATTERN CL = 50pF

104

103

VDD = 5V

102

CL = 15pF

VDD = 15V VDD = 10V TEST CIRCUIT VDD f 9 4 CL 100Ω 3 12 5 13 100Ω CD4053 2 10 1 15 11 14 6 7 8

Ι

10 1

10


105


CD4051B, CD4052B, CD4053B Test Circuits and Waveforms VDD = 15V

VDD = 7.5V

VDD = 5V

VDD = 5V

5V

7.5V 16

5V

16

16

16

VSS = 0V

VSS = 0V

VSS = 0V VEE = 0V

7 8

VEE = -7.5V

7 8

VEE = -10V

7 8

7 8

VEE = -5V

VSS = 0V (D)

(C)

(B)

(A)

NOTE: The ADDRESS (digital-control inputs) and INHIBIT logic levels are: “0” = VSS and “1” = VDD. The analog signal (through the TG) may swing from VEE to VDD. FIGURE 9. TYPICAL BIAS VOLTAGES

tr = 20ns

tr = 20ns

tf = 20ns

90% 50%

90% 50%

10%

tf = 20ns

90% 50%

90% 50% 10%

10%

10% TURN-ON TIME 90% 50%

90% 10%

10%

10% TURN-OFF TIME

TURN-OFF TIME

FIGURE 10. WAVEFORMS, CHANNEL BEING TURNED ON (RL = 1kΩ)

FIGURE 11. WAVEFORMS, CHANNEL BEING TURNED OFF (RL = 1kΩ)

VDD

VDD

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9 CD4051

IDD

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9 CD4052

VDD

IDD

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9 CD4053

FIGURE 12. OFF CHANNEL LEAKAGE CURRENT - ANY CHANNEL OFF

9

TURN-ON TIME

tPHZ

IDD

CD4051B, CD4052B, CD4053B Test Circuits and Waveforms (Continued) VDD

1 2 3 4 5 6 7 8

IDD

VDD

16 15 14 13 12 11 10 9

1 2 3 4 5 6 7 8

IDD

VDD

16 15 14 13 12 11 10 9

1 2 3 4 5 6 7 8

CD4052

CD4051

16 15 14 13 12 11 10 9

IDD

CD4053

FIGURE 13. OFF CHANNEL LEAKAGE CURRENT - ALL CHANNELS OFF

VDD 1 2 3 4 5 6 7 8

VDD

VEE VSS

16 15 14 13 12 11 10 9

OUTPUT

VDD

OUTPUT

OUTPUT

1 RL CL 2 RL CL 3 VDD VEE 4 VDD 5 VEE 6 VEE VSS CLOCK 7 IN 8 VSS

VSS

CD4051

16 15 14 13 12 11 10 9

VDD

VEE

VDD

VSS CLOCK VSS IN VSS

CD4052

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9 CD4053

RL

CL VEE

VDD

VSS CLOCK IN VSS

FIGURE 14. PROPAGATION DELAY - ADDRESS INPUT TO SIGNAL OUTPUT

VDD

OUTPUT RL

1 2 3 4 5 6 7 8

50pF VEE

VDD VSS

VDD CLOCK VEE IN VSS

16 15 14 13 12 11 10 9

VDD

OUTPUT 50pF

RL

VEE VDD VSS

VDD CLOCK VEE IN VSS

tPHL AND tPLH VSS CD4051

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9

OUTPUT RL

50pF VEE VDD

VDD VSS CLOCK VEE IN VSS

V tPHL AND tPLH SS CD4052

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9

VDD

V tPHL AND tPLH SS CD4053

FIGURE 15. PROPAGATION DELAY - INHIBIT INPUT TO SIGNAL OUTPUT VDD

VIH

1K

VIH VIL

VDD

VDD

µA

1K

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9

VIH VIL

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9

1K

1K

µA VIH

1K

VIL VIH

VIL

MEASURE < 2µA ON ALL “OFF” CHANNELS (e.g., CHANNEL 6)

1K

µA

VIH VIL

VIL MEASURE < 2µA ON ALL “OFF” CHANNELS (e.g., CHANNEL 2x)

MEASURE < 2µA ON ALL “OFF” CHANNELS (e.g., CHANNEL by)

FIGURE 16. INPUT VOLTAGE TEST CIRCUITS (NOISE IMMUNITY)

10

16 15 14 13 12 11 10 9

CD4053B

CD4052B

CD4051B

1 2 3 4 5 6 7 8

CD4051B, CD4052B, CD4053B Test Circuits and Waveforms (Continued) VDD

VDD 1 2 3 4 5 6 7 8 Ι

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9 Ι

CD4051 CD4053

VDD

16 15 14 13 12 11 10 9

KEITHLEY 160 DIGITAL MULTIMETER TG “ON”

10kΩ

X-Y PLOTTER

FIGURE 18. CHANNEL ON RESISTANCE MEASUREMENT CIRCUIT

VDD 1 2 3 4 5 6 7 8

VDD Ι VSS

CD4051 CD4053

VSS

X

H.P. MOSELEY 7030A

CD4052

VDD 16 15 14 13 12 11 10 9

Y

VSS

FIGURE 17. QUIESCENT DEVICE CURRENT

1 2 3 4 5 6 7 8

1kΩ RANGE

VSS

16 15 14 13 12 11 10 9

VDD Ι VSS

CD4052

NOTE: Measure inputs sequentially, to both VDD and VSS connect all unused inputs to either VDD or VSS .

NOTE: Measure inputs sequentially, to both VDD and VSS connect all unused inputs to either VDD or VSS .

FIGURE 19. INPUT CURRENT

5VP-P

CHANNEL ON 5VP-P

OFF CHANNEL VDD

RF VM

RL

1K

RL

RL

RL

FIGURE 20. FEEDTHROUGH (ALL TYPES)

FIGURE 21. CROSSTALK BETWEEN ANY TWO CHANNELS (ALL TYPES)

CHANNEL IN Y ON OR OFF

CHANNEL IN X ON OR OFF RL

RF VM RL

FIGURE 22. CROSSTALK BETWEEN DUALS OR TRIPLETS (CD4052B, CD4053B)

11

RF VM

CHANNEL ON

RF VM

CHANNEL OFF

6 7 8

5VP-P

COMMON

CHANNEL OFF

CD4051B, CD4052B, CD4053B Test Circuits and Waveforms (Continued) DIFFERENTIAL SIGNALS

CD4052

CD4052

COMMUNICATIONS LINK

DIFF. AMPLIFIER/ LINE DRIVER

DIFF. MULTIPLEXING

DIFF. RECEIVER

DEMULTIPLEXING

FIGURE 23. TYPICAL TIME-DIVISION APPLICATION OF THE CD4052B

Special Considerations In applications where separate power sources are used to drive VDD and the signal inputs, the VDD current capability should exceed VDD/RL (RL = effective external load). This provision avoids permanent current flow or clamp action on the VDD supply when power is applied or removed from the CD4051B, CD4052B or CD4053B.

A B CD4051B C INH

A B C

D E

Q0

A B E

1/2 CD4556

A B CD4051B C INH

Q1 Q2

A B CD4051B C INH

FIGURE 24. 24-TO-1 MUX ADDRESSING

12

COMMON OUTPUT

IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to , before placing orders, that information being relied on is current and complete. All products are sold subject to the and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.



































[ /Title (CD40 70B, CD407 7B) /Subject (CMO S Quad ExclusiveOR and ExclusiveNOR Gate) /Autho r () /Keywords (Harris Semiconductor, CD400 0, metal gate, CMOS , pdip, cerdip, mil,

CD4070B, CD4077B


CMOS Quad Exclusive-OR and Exclusive-NOR Gate

January 1998

Features

Description

• High-Voltage Types (20V Rating)

The Harris CD4070B contains four independent ExclusiveOR gates. The Harris CD4077B contains four independent Exclusive-NOR gates.

• CD4070B - Quad Exclusive-OR Gate • CD4077B - Quad Exclusive-NOR Gate

The CD4070B and CD4077B provide the system designer with a means for direct implementation of the Exclusive-OR and Exclusive-NOR functions, respectively.

• Medium Speed Operation - tPHL, tPLH = 65ns (Typ) at VDD = 10V, CL = 50pF • 100% Tested for Quiescent Current at 20V

Ordering Information

• Standardized Symmetrical Output Characteristics • 5V, 10V and 15V Parametric Ratings

PART NUMBER

• Maximum Input Current of 1µA at 18V Over Full Package Temperature Range - 100nA at 18V and 25oC • Noise Margin (Over Full Package Temperature Range) - 1V at VDD = 5V, 2V at VDD = 10V, 2.5V at VDD = 15V • Meets All Requirements of JEDEC Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices

Applications

TEMP. RANGE (oC)

PACKAGE

PKG. NO.

CD4070BE

-55 to 125

14 Ld PDIP

E14.3

CD4077BE

-55 to 125

14 Ld PDIP

E14.3

CD4070BF

-55 to 125

14 Ld CERDIP

F14.3

CD4077BF

-55 to 125

14 Ld CERDIP

F14.3

CD4070BM

-55 to 125

14 Ld SOIC

M14.15

CD4077BM

-55 to 125

14 Ld SOIC

M14.15

• Logical Comparators • Adders/Subtractors • Parity Generators and Checkers

Pinouts CD4070B (PDIP, CERDIP, SOIC) TOP VIEW

CD4077B (PDIP, CERDIP, SOIC) TOP VIEW

A 1

14 VDD

A 1

14 VDD

B 2

13 H

B 2

13 H

J=A⊕B 3

12 G

J=A⊕B 3

12 G

K=C⊕D 4

11 M = G ⊕ H

K=C⊕D 4

11 M = G ⊕ H

C 5

10 L = E ⊕ F

C 5

10 L = E ⊕ F

D 6

9 F

D 6

9 F

VSS 7

8 E

VSS 7

8 E

CAUTION: These devices are sensitive to electrostatic discharge. s should follow proper IC Handling Procedures. Copyright

© Harris Corporation 1998

1

File Number

910.1

CD4070B, CD4077B Functional Diagrams CD4070B 1

A J=A⊕B K=C⊕D M=G⊕ H L=E⊕F

VSS = 7 VDD = 14

5

C

4

6

D

8

E

10

9

F

H

3

2

B

G

CD4077B

12

11

13

A

J

B J =A K=C

K

L

⊕B ⊕D

⊕H =E⊕F

C D

M=G

E

L

F G

M

H

1

3

2 5

4

6 8

10

9 12

11

13

J

K

L

M

VDD VDD VDD

p VDD

B†

p

2(5,9,12)

n

p

1(6,8,13)

n

p

n

J

p n

3(4,10,11) n

VDD

n

p

p J

VDD

p

VSS

†

n VSS

VDD A†

2(5,9,12)

n

VSS

p

B†

p

A†

p

1(6,8,13)

n

n

VSS

VSS

†

INPUTS PROTECTED BY CMOS PROTECTION NETWORK

3(4,10,11)

n

VSS

VDD


VSS

VSS

FIGURE 1. SCHEMATIC DIAGRAM FOR CD4070B (1 OF 4 IDENTICAL GATES)


CD4070B TRUTH TABLE (1 OF 4 GATES)


A

B

J

A

B

J

0

0

0

0

0

1

1

0

1

1

0

0

0

1

1

0

1

0

1

1

0

1

1

1

NOTE: 1 = High Level 0 = Low Level J=A⊕B


2

CD4070B, CD4077B Absolute Maximum Ratings

Thermal Information

DC Supply Voltage Range (VDD) . . . . . . . . . . . . . . . . . -0.5V to 20V Input Voltage Range, All Inputs . . . . . . . . . . . . . . -0.5V to VDD 0.5V DC Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .± 10mA

Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 90 N/A CERDIP Package . . . . . . . . . . . . . . . . 95 38 SOIC Package . . . . . . . . . . . . . . . . . . . 175 N/A Maximum Junction Temperature (Hermetic Package or Die)175oC Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Operating Conditions Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range (Typical) . . . . . . . . . . . . . . . . . . . . 3V to 18V


NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Specifications LIMITS AT INDICATED TEMPERATURES (oC) CONDITIONS

PARAMETER Quiescent Device Current IDD Max

Output Low (Sink) Current IOL Min

Output High (Source) Current IOH Min

Output Voltage: Low Level, VOL Max

Output Voltage: High Level, VOH Min

Input Low Voltage, VIL Max

Input High Voltage, VIH Min

Input Current, IIN Max

25

VO (V)

VIN (V)

VDD (V)

-55

-40

85

125

MIN

TYP

MAX

UNITS

-

0, 5

5

0.25

0.25

7.5

7.5

-

0.01

0.25

µA

-

0, 10

10

0.5

0.5

15

15

-

0.01

0.5

µA

-

0, 15

15

1

1

30

30

-

0.01

1

µA

-

0, 20

20

5

5

150

150

-

0.02

5

µA

0.4

0, 5

5

0.64

0.61

0.42

0.36

0.51

1

-

mA

0.5

0, 10

10

1.6

1.5

1.1

0.9

1.3

2.6

-

mA

1.5

0, 15

15

4.2

4

2.8

2.4

3.4

6.8

-

mA

4.6

0, 5

5

-0.64

-0.61

-0.42

-0.36

-0.51

-1

-

mA

2.5

0, 5

5

-2

-1.8

-1.3

-1.15

-1.6

-3.2

-

mA

9.5

0, 10

10

-1.6

-1.5

-1.1

-0.9

-1.3

-2.6

-

mA

13.5

0, 15

15

-4.2

-4

-2.8

-2.4

-3.4

-6.8

-

mA

-

0, 5

5

0.05

0.05

0.05

0.05

-

0

0.05

V

-

0, 10

10

0.05

0.05

0.05

0.05

-

0

0.05

V

-

0, 15

15

0.05

0.05

0.05

0.05

-

0

0.05

V

-

0, 5

5

4.95

4.95

4.95

4.95

4.95

5

-

V

-

0, 10

10

9.95

9.95

9.95

9.95

9.95

10

-

V

-

0, 15

15

14.95

14.95

14.95

14.95

14.95

15

-

V

0.5, 4.5

-

5

1.5

1.5

1.5

1.5

-

-

1.5

V

1, 9

-

10

3

3

3

3

-

-

3

V

1.5, 13.5

-

15

4

4

4

4

-

-

4

V

0.5, 4.5

-

5

3.5

3.5

3.5

3.5

3.5

-

-

V

1, 9

-

10

7

7

7

7

7

-

-

V

1.5, 13.5

-

15

11

11

11

11

11

-

-

V

-

0, 18

18

±0.1

±0.1

±1

±1

-

±10-5

±0.1

µA

3

CD4070B, CD4077B AC Electrical Specifications

TA = 25oC, Input tr, tf = 20ns, CL = 50pF, RL = 200kΩ TEST CONDITIONS

PARAMETER Propagation Delay Time

Transition Time

SYMBOL

VDD (V)

TYP

MAX

UNITS

tPHL, tPLH

5

140

280

ns

10

65

130

ns

15

50

100

ns

5

100

200

ns

10

50

100

ns

15

40

80

ns

Any Input

5

7.5

pF

tTHL, tTLH

Input Capacitance

LIMITS ON ALL TYPES

CIN

TA = 25oC

IOL, OUTPUT LOW (SINK) CURRENT (mA)

GATE TO SOURCE VOLTAGE (VGS) = 15V

30 25 20

10V 15 10 5V 5 0 0

5

10

15

TA = 25oC

15 GATE TO SOURCE VOLTAGE (VGS) = 15V

12.5 10

10V 7.5 5 5V

2.5 0 0

5

VDS, DRAIN TO SOURCE VOLTAGE (V)

10

15





-15

-10

-5

TA = 25oC GATE TO SOURCE VOLTAGE (VGS) = -5V

0

0 -5 -10 -15

-10V

-20 -25

-15V

-30

IOH, OUTPUT HIGH (SOURCE) CURRENT (mA)

FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS

-15

-10

-5

0 0


-5

-10V

-15V


-10

-15


4

IOH, OUTPUT HIGH (SINK) CURRENT (mA)


Typical Performance Curves

CD4070B, CD4077B (Continued)

tPHL, tPLH, PROPAGATION DELAY TIME (ns)

tTHL, tTLH, TRANSITION TIME (ns)

Typical Performance Curves TA = 25oC

200 SUPPLY VOLTAGE (VDD) = 5V 150 100

10V

50

15V

0 0

20

40

60

80

100

TA = 25oC

300

200


100 10V 15V 0 0

110

20

105

TA = 25oC LOAD CAPACITANCE CL = 50pF 300

200

100

0 5

10

15

80

60

100

FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE

PD, POWER DISSIPATION (µW)


FIGURE 7. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE

0

40

CL, LOAD CAPACITANCE (pF)


VDD, SUPPLY VOLTAGE (V)

FIGURE 9. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF SUPPLY VOLTAGE

V

104

)=

15

D

E AG LT O YV PL

103 102

(V D

P

SU

10

10V CL = 50pF 10V CL = 15pF

5V

1 10-1 10-1

20

TA = 25oC

1

102 103 10 fI, INPUT FREQUENCY (kHz)

104

FIGURE 10. TYPICAL DYNAMIC POWER DISSIPATION AS A FUNCTION OF INPUT FREQUENCY

5

CD4070B, CD4077B Dual-In-Line Plastic Packages (PDIP) E14.3 (JEDEC MS-001-AA ISSUE D)

N

14 LEAD DUAL-IN-LINE PLASTIC PACKAGE

E1 INDEX AREA

1 2 3

INCHES

N/2

MILLIMETERS

SYMBOL

MIN

MAX

MIN

MAX

NOTES

A

-

0.210

-

5.33

4

A1

0.015

-

0.39

-

4

A2

0.115

0.195

2.93

4.95

-

-B-AE

D BASE PLANE

A2

-C-

SEATING PLANE

A L

D1

e

B1

D1

B 0.010 (0.25) M

A1

eC C A B S

B

0.014

0.022

0.356

0.558

-

C L

B1

0.045

0.070

1.15

1.77

8

eA

C

0.008

0.014

D

0.735

0.775

C

eB

NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 1.14mm).

6

0.204

0.355

18.66

19.68

5

D1

0.005

-

0.13

-

5

E

0.300

0.325

7.62

8.25

6

E1

0.240

0.280

6.10

7.11

5

e

0.100 BSC

eA

0.300 BSC

eB

-

L

0.115

N

14

2.54 BSC

-

7.62 BSC

6

0.430

-

0.150

2.93 14

10.92

7

3.81

4 9 Rev. 0 12/93

CD4070B, CD4077B Ceramic Dual-In-Line Frit Seal Packages (CERDIP) c1

F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A)

LEAD FINISH

14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE

-D-

-A-

BASE METAL

INCHES

(c)

SYMBOL

E M -Bbbb S

C A-B S

Q -C-

SEATING PLANE S1

-

0.200

-

5.08

-

0.014

0.026

0.36

0.66

2

b1

0.014

0.023

0.36

0.58

3

b2

0.045

0.065

1.14

1.65

-

b3

0.023

0.045

0.58

1.14

4

c

0.008

0.018

0.20

0.46

2

c1

0.008

0.015

0.20

0.38

3

D

-

0.785

-

19.94

5

E

0.220

0.310

5.59

7.87

5

eA

b2 b ccc M

C A-B S

e D S

eA/2

NOTES

b

α

A A

MAX

A

A L

MIN

M (b)

D BASE PLANE

MILLIMETERS

MAX

b1

SECTION A-A

D S

MIN

c

aaa M C A - B S D S

NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH.

e

0.100 BSC

2.54 BSC

-

eA

0.300 BSC

7.62 BSC

-

eA/2

0.150 BSC

3.81 BSC

-

L

0.125

0.200

3.18

5.08

-

Q

0.015

0.060

0.38

1.52

6

S1

0.005

-

0.13

-

7

α

90o

105o

90o

105o

-

aaa

-

0.015

-

0.38

-

bbb

-

0.030

-

0.76

-

ccc

-

0.010

-

0.25

-

M

-

0.0015

-

0.038

2, 3

N

14

14

8 Rev. 0 4/94

7




[ /Title (CD40 70B, CD407 7B) /Subject (CMO S Quad ExclusiveOR and ExclusiveNOR Gate) /Autho r () /Keywords (Harris Semiconductor, CD400 0, metal gate, CMOS , pdip, cerdip, mil,

CD4070B, CD4077B


CMOS Quad Exclusive-OR and Exclusive-NOR Gate

January 1998

Features

Description

• High-Voltage Types (20V Rating)

The Harris CD4070B contains four independent ExclusiveOR gates. The Harris CD4077B contains four independent Exclusive-NOR gates.

• CD4070B - Quad Exclusive-OR Gate • CD4077B - Quad Exclusive-NOR Gate

The CD4070B and CD4077B provide the system designer with a means for direct implementation of the Exclusive-OR and Exclusive-NOR functions, respectively.

• Medium Speed Operation - tPHL, tPLH = 65ns (Typ) at VDD = 10V, CL = 50pF • 100% Tested for Quiescent Current at 20V

Ordering Information

• Standardized Symmetrical Output Characteristics • 5V, 10V and 15V Parametric Ratings

PART NUMBER

• Maximum Input Current of 1µA at 18V Over Full Package Temperature Range - 100nA at 18V and 25oC • Noise Margin (Over Full Package Temperature Range) - 1V at VDD = 5V, 2V at VDD = 10V, 2.5V at VDD = 15V • Meets All Requirements of JEDEC Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices

Applications

TEMP. RANGE (oC)

PACKAGE

PKG. NO.

CD4070BE

-55 to 125

14 Ld PDIP

E14.3

CD4077BE

-55 to 125

14 Ld PDIP

E14.3

CD4070BF

-55 to 125

14 Ld CERDIP

F14.3

CD4077BF

-55 to 125

14 Ld CERDIP

F14.3

CD4070BM

-55 to 125

14 Ld SOIC

M14.15

CD4077BM

-55 to 125

14 Ld SOIC

M14.15

• Logical Comparators • Adders/Subtractors • Parity Generators and Checkers

Pinouts CD4070B (PDIP, CERDIP, SOIC) TOP VIEW

CD4077B (PDIP, CERDIP, SOIC) TOP VIEW

A 1

14 VDD

A 1

14 VDD

B 2

13 H

B 2

13 H

J=A⊕B 3

12 G

J=A⊕B 3

12 G

K=C⊕D 4

11 M = G ⊕ H

K=C⊕D 4

11 M = G ⊕ H

C 5

10 L = E ⊕ F

C 5

10 L = E ⊕ F

D 6

9 F

D 6

9 F

VSS 7

8 E

VSS 7

8 E

CAUTION: These devices are sensitive to electrostatic discharge. s should follow proper IC Handling Procedures. Copyright

© Harris Corporation 1998

1

File Number

910.1

CD4070B, CD4077B Functional Diagrams CD4070B 1

A J=A⊕B K=C⊕D M=G⊕ H L=E⊕F

VSS = 7 VDD = 14

5

C

4

6

D

8

E

10

9

F

H

3

2

B

G

CD4077B

12

11

13

A

J

B J =A K=C

K

L

⊕B ⊕D

⊕H =E⊕F

C D

M=G

E

L

F G

M

H

1

3

2 5

4

6 8

10

9 12

11

13

J

K

L

M

VDD VDD VDD

p VDD

B†

p

2(5,9,12)

n

p

1(6,8,13)

n

p

n

J

p n

3(4,10,11) n

VDD

n

p

p J

VDD

p

VSS

†

n VSS

VDD A†

2(5,9,12)

n

VSS

p

B†

p

A†

p

1(6,8,13)

n

n

VSS

VSS

†


3(4,10,11)

n

VSS

VDD


VSS

VSS





A

B

J

A

B

J

0

0

0

0

0

1

1

0

1

1

0

0

0

1

1

0

1

0

1

1

0

1

1

1



2

CD4070B, CD4077B Absolute Maximum Ratings

Thermal Information

DC Supply Voltage Range (VDD) . . . . . . . . . . . . . . . . . -0.5V to 20V Input Voltage Range, All Inputs . . . . . . . . . . . . . . -0.5V to VDD 0.5V DC Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .± 10mA

Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 90 N/A CERDIP Package . . . . . . . . . . . . . . . . 95 38 SOIC Package . . . . . . . . . . . . . . . . . . . 175 N/A Maximum Junction Temperature (Hermetic Package or Die)175oC Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Operating Conditions Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range (Typical) . . . . . . . . . . . . . . . . . . . . 3V to 18V


NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Specifications LIMITS AT INDICATED TEMPERATURES (oC) CONDITIONS

PARAMETER Quiescent Device Current IDD Max

Output Low (Sink) Current IOL Min

Output High (Source) Current IOH Min

Output Voltage: Low Level, VOL Max

Output Voltage: High Level, VOH Min

Input Low Voltage, VIL Max

Input High Voltage, VIH Min

Input Current, IIN Max

25

VO (V)

VIN (V)

VDD (V)

-55

-40

85

125

MIN

TYP

MAX

UNITS

-

0, 5

5

0.25

0.25

7.5

7.5

-

0.01

0.25

µA

-

0, 10

10

0.5

0.5

15

15

-

0.01

0.5

µA

-

0, 15

15

1

1

30

30

-

0.01

1

µA

-

0, 20

20

5

5

150

150

-

0.02

5

µA

0.4

0, 5

5

0.64

0.61

0.42

0.36

0.51

1

-

mA

0.5

0, 10

10

1.6

1.5

1.1

0.9

1.3

2.6

-

mA

1.5

0, 15

15

4.2

4

2.8

2.4

3.4

6.8

-

mA

4.6

0, 5

5

-0.64

-0.61

-0.42

-0.36

-0.51

-1

-

mA

2.5

0, 5

5

-2

-1.8

-1.3

-1.15

-1.6

-3.2

-

mA

9.5

0, 10

10

-1.6

-1.5

-1.1

-0.9

-1.3

-2.6

-

mA

13.5

0, 15

15

-4.2

-4

-2.8

-2.4

-3.4

-6.8

-

mA

-

0, 5

5

0.05

0.05

0.05

0.05

-

0

0.05

V

-

0, 10

10

0.05

0.05

0.05

0.05

-

0

0.05

V

-

0, 15

15

0.05

0.05

0.05

0.05

-

0

0.05

V

-

0, 5

5

4.95

4.95

4.95

4.95

4.95

5

-

V

-

0, 10

10

9.95

9.95

9.95

9.95

9.95

10

-

V

-

0, 15

15

14.95

14.95

14.95

14.95

14.95

15

-

V

0.5, 4.5

-

5

1.5

1.5

1.5

1.5

-

-

1.5

V

1, 9

-

10

3

3

3

3

-

-

3

V

1.5, 13.5

-

15

4

4

4

4

-

-

4

V

0.5, 4.5

-

5

3.5

3.5

3.5

3.5

3.5

-

-

V

1, 9

-

10

7

7

7

7

7

-

-

V

1.5, 13.5

-

15

11

11

11

11

11

-

-

V

-

0, 18

18

±0.1

±0.1

±1

±1

-

±10-5

±0.1

µA

3

CD4070B, CD4077B AC Electrical Specifications

TA = 25oC, Input tr, tf = 20ns, CL = 50pF, RL = 200kΩ TEST CONDITIONS

PARAMETER Propagation Delay Time

Transition Time

SYMBOL

VDD (V)

TYP

MAX

UNITS

tPHL, tPLH

5

140

280

ns

10

65

130

ns

15

50

100

ns

5

100

200

ns

10

50

100

ns

15

40

80

ns

Any Input

5

7.5

pF

tTHL, tTLH

Input Capacitance

LIMITS ON ALL TYPES

CIN

TA = 25oC


GATE TO SOURCE VOLTAGE (VGS) = 15V

30 25 20

10V 15 10 5V 5 0 0

5

10

15

TA = 25oC

15 GATE TO SOURCE VOLTAGE (VGS) = 15V

12.5 10

10V 7.5 5 5V

2.5 0 0

5


10

15





-15

-10

-5


0

0 -5 -10 -15

-10V

-20 -25

-15V

-30

IOH, OUTPUT HIGH (SOURCE) CURRENT (mA)

FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS

-15

-10

-5

0 0


-5

-10V

-15V


-10

-15


4

IOH, OUTPUT HIGH (SINK) CURRENT (mA)


Typical Performance Curves

CD4070B, CD4077B (Continued)


tTHL, tTLH, TRANSITION TIME (ns)

Typical Performance Curves TA = 25oC

200 SUPPLY VOLTAGE (VDD) = 5V 150 100

10V

50

15V

0 0

20

40

60

80

100

TA = 25oC

300

200


100 10V 15V 0 0

110

20

105

TA = 25oC LOAD CAPACITANCE CL = 50pF 300

200

100

0 5

10

15

80

60

100

FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE

PD, POWER DISSIPATION (µW)


FIGURE 7. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE

0

40



VDD, SUPPLY VOLTAGE (V)

FIGURE 9. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF SUPPLY VOLTAGE

V

104

)=

15

D

E AG LT O YV PL

103 102

(V D

P

SU

10

10V CL = 50pF 10V CL = 15pF

5V

1 10-1 10-1

20

TA = 25oC

1

102 103 10 fI, INPUT FREQUENCY (kHz)

104

FIGURE 10. TYPICAL DYNAMIC POWER DISSIPATION AS A FUNCTION OF INPUT FREQUENCY

5

CD4070B, CD4077B Dual-In-Line Plastic Packages (PDIP) E14.3 (JEDEC MS-001-AA ISSUE D)

N

14 LEAD DUAL-IN-LINE PLASTIC PACKAGE

E1 INDEX AREA

1 2 3

INCHES

N/2

MILLIMETERS

SYMBOL

MIN

MAX

MIN

MAX

NOTES

A

-

0.210

-

5.33

4

A1

0.015

-

0.39

-

4

A2

0.115

0.195

2.93

4.95

-

-B-AE

D BASE PLANE

A2

-C-

SEATING PLANE

A L

D1

e

B1

D1

B 0.010 (0.25) M

A1

eC C A B S

B

0.014

0.022

0.356

0.558

-

C L

B1

0.045

0.070

1.15

1.77

8

eA

C

0.008

0.014

D

0.735

0.775

C

eB

NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 1.14mm).

6

0.204

0.355

18.66

19.68

5

D1

0.005

-

0.13

-

5

E

0.300

0.325

7.62

8.25

6

E1

0.240

0.280

6.10

7.11

5

e

0.100 BSC

eA

0.300 BSC

eB

-

L

0.115

N

14

2.54 BSC

-

7.62 BSC

6

0.430

-

0.150

2.93 14

10.92

7

3.81

4 9 Rev. 0 12/93

CD4070B, CD4077B Ceramic Dual-In-Line Frit Seal Packages (CERDIP) c1

F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A)

LEAD FINISH

14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE

-D-

-A-

BASE METAL

INCHES

(c)

SYMBOL

E M -Bbbb S

C A-B S

Q -C-

SEATING PLANE S1

-

0.200

-

5.08

-

0.014

0.026

0.36

0.66

2

b1

0.014

0.023

0.36

0.58

3

b2

0.045

0.065

1.14

1.65

-

b3

0.023

0.045

0.58

1.14

4

c

0.008

0.018

0.20

0.46

2

c1

0.008

0.015

0.20

0.38

3

D

-

0.785

-

19.94

5

E

0.220

0.310

5.59

7.87

5

eA

b2 b ccc M

C A-B S

e D S

eA/2

NOTES

b

α

A A

MAX

A

A L

MIN

M (b)

D BASE PLANE

MILLIMETERS

MAX

b1

SECTION A-A

D S

MIN

c

aaa M C A - B S D S

NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH.

e

0.100 BSC

2.54 BSC

-

eA

0.300 BSC

7.62 BSC

-

eA/2

0.150 BSC

3.81 BSC

-

L

0.125

0.200

3.18

5.08

-

Q

0.015

0.060

0.38

1.52

6

S1

0.005

-

0.13

-

7

α

90o

105o

90o

105o

-

aaa

-

0.015

-

0.38

-

bbb

-

0.030

-

0.76

-

ccc

-

0.010

-

0.25

-

M

-

0.0015

-

0.038

2, 3

N

14

14

8 Rev. 0 4/94

7




CD4071BM/CD4071BC Quad 2-Input OR Buffered B Series Gate CD4081BM/CD4081BC Quad 2-Input AND Buffered B Series Gate General Description

Features

These quad gates are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. They have equal source and sink current capabilities and conform to standard B series output drive. The devices also have buffered outputs which improve transfer characteristics by providing very high gain. All inputs protected against static discharge with diodes to VDD and VSS.

Y

Y Y Y

Low power TTL Fan out of 2 driving 74L compatibility or 1 driving 74LS 5V – 10V – 15V parametric ratings Symmetrical output characteristics Maximum input leakage 1 mA at 15V over full temperature range

Connection Diagrams CD4071B Dual-In-Line Package

TL/F/5977 – 3

Top View CD4081B Dual-In-Line Package

TL/F/5977 – 6

Top View Order Number CD4071B or CD4081B


TL/F/5977


CD4071BM/CD4071BC Quad 2-Input OR Buffered B Series Gate CD4081BM/CD4081BC Quad 2-Input AND Buffered B Series Gate

February 1988

Absolute Maximum Ratings (Notes 1 & 2) If Military/Aerospace specified devices are required, please the National Semiconductor Sales Office/Distributors for availability and specifications.


Voltage at Any Pin

b 0.5V to VDD a 0.5V

Operating Conditions

700 mW 500 mW

Operating Range (VDD) Operating Temperature Range (TA) CD4071BM, CD4081BM CD4071BC, CD4081BC

Power Dissipation (PD) Dual-In-Line Small Outline VDD Range Storage Temperature (TS)

b 0.5 VDC to a 18 VDC b 65§ C to a 150§ C

260§ C

3 VDC to 15 VDC b 55§ C to a 125§ C b 40§ C to a 85§ C

DC Electrical Characteristics CD4071BM/CD4081BM (Note 2) Symbol

Parameter

b 55§ C

Conditions

Min

Max

a 25§ C

Min

a 125§ C

Min

Units

Typ

Max

Max

0.25 0.50 1.0

0.004 0.005 0.006

0.25 0.50 1.0

7.5 15 30

mA mA mA

0.05 0.05 0.05

0 0 0

0.05 0.05 0.05

0.05 0.05 0.05

V V V

IDD



VOL





VIL



VIH



3.5 7.0 11.0

3.5 7.0 11.0

3 6 9

3.5 7.0 11.0

V V V

IOL



0.64 1.6 4.2

0.51 1.3 3.4

0.88 2.25 8.8

0.36 0.9 2.4

mA mA mA

IOH



b 0.64 b 1.6 b 4.2

b 0.51 b 1.3 b 3.4

b 0.88 b 2.25 b 8.8

b 0.36 b 0.9 b 2.4

mA mA mA

IIN

Input Current


VOH

( (

lIOl k 1 mA lIOl k 1 mA

4.95 9.95 14.95

4.95 9.95 14.95 1.5 3.0 4.0

5 10 15 2 4 6

4.95 9.95 14.95 1.5 3.0 4.0

V V V 1.5 3.0 4.0

b 0.10

b 10 b 5

b 0.10

b 1.0

0.10

10b5

0.10

1.0

V V V

mA mA

Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation. Note 2: All voltages measured with respect to VSS unless otherwise specified. Note 3: IOH and IOL are tested one output at a time.

2

DC Electrical Characteristics CD4071BC/CD4081BC (Note 2) Symbol

Parameter

b 40§ C

Conditions

Min

a 25§ C

Max

Min

a 85§ C

Min

Units

Typ

Max

Max

1 2 4

0.004 0.005 0.006

1 2 4

7.5 15 30

mA mA mA

0.05 0.05 0.05

0 0 0

0.05 0.05 0.05

0.05 0.05 0.05

V V V

IDD



VOL





VIL



VIH



3.5 7.0 11.0

3.5 7.0 11.0

3 6 9

3.5 7.0 11.0

V V V

IOL



0.52 1.3 3.6

0.44 1.1 3.0

0.88 2.25 8.8

0.36 0.9 2.4

mA mA mA

IOH



b 0.52 b 1.3 b 3.6

b 0.44 b 1.1 b 3.0

b 0.88 b 2.25 b 8.8

b 0.36 b 0.9 b 2.4

mA mA mA

IIN

Input Current


VOH

( (

lIOl k 1 mA lIOl k 1 mA

4.95 9.95 14.95

4.95 9.95 14.95

5 10 15

1.5 3.0 4.0

2 4 6

4.95 9.95 14.95 1.5 3.0 4.0

V V V 1.5 3.0 4.0

V V V

b 0.30

b 10 b 5

b 0.30

b 1.0

0.30

10b5

0.30

1.0

mA mA

AC Electrical Characteristics* CD4071BC/CD4071BM TA e 25§ C, Input tr; tf e 20 ns, CL e 50 pF, RL e 200 kX, Typical temperature coefficient is 0.3%/§ C Symbol

Parameter

Conditions

Typ

Max

Units

100 40 30

250 100 70

ns ns ns

tPHL

Propagation Delay Time, High-to-Low Level


tPLH

Propagation Delay Time, Low-to-High Level


90 40 30

250 100 70

ns ns ns

tTHL, tTLH

Transition Time


90 50 40

200 100 80

ns ns ns

CIN


Any Input

5

7.5

pF

D

Power Dissipation Capacity

Any Gate

18

pF

*AC Parameters are guaranteed by DC correlated testing. Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation. Note 2: All voltages measured with respect to VSS unless otherwise specified. Note 3: IOH and IOL are tested one output at a time.

3

AC Electrical Characteristics* CD4081BC/CD4081BM TA e 25§ C, Input tr; tf e 20 ns, CL e 50 pF, RL e 200 kX, Typical temperature coefficient is 0.3%/§ C Conditions

Typ

Max

Units

tPHL

Symbol

Propagation Delay Time, High-to-Low Level

Parameter


100 40 30

250 100 70

ns ns ns

tPLH

Propagation Delay Time, Low-to-High Level


120 50 35

250 100 70

ns ns ns

tTHL, tTLH

Transition Time


90 50 40

200 100 80

ns ns ns

CIN


Any Input

5

7.5

pF

D

Power Dissipation Capacity

Any Gate

18

pF



TL/F/5977–7

FIGURE 1. Typical Transfer Characteristics

TL/F/5977 – 8


TL/F/5977 – 9


TL/F/5977 – 11

FIGURE 5 TL/F/5977–10


4

TL/F/5977 – 12

FIGURE 6

Typical Performance Characteristics (Continued)

TL/F/5977–13

FIGURE 7

TL/F/5977 – 15

TL/F/5977 – 14

FIGURE 9

FIGURE 8

TL/F/5977–16

FIGURE 10

TL/F/5977 – 18

TL/F/5977 – 17

FIGURE 11

FIGURE 12

TL/F/5977 – 19

TL/F/5977 – 20

FIGURE 13

FIGURE 14

5

Schematic Diagrams CD4071B

(/4 of device shown JeAaB Logical ‘‘1’’ e High Logical ‘‘0’’ e Low *All inputs protected by standard CMOS protection circuit.

TL/F/5977 – 2

TL/F/5977–1

CD4081B

(/4 of device shown JeA#B Logical ‘‘1’’ e High Logical ‘‘0’’ e Low *All inputs protected by standard CMOS protection circuit.

TL/F/5977 – 5

TL/F/5977–4

6


Ceramic Dual-In-Line Package (J) Order Number CD4071BMJ, CD4071BCJ CD4081BMJ or CD4081BCJ NS Package Number J14A

7

CD4071BM/CD4071BC Quad 2-Input OR Buffered B Series Gate CD4081BM/CD4081BC Quad 2-Input AND Buffered B Series Gate


Molded Dual-In-Line Package (N) Order Number CD4071BMN, CD4071BCN CD4081BMN or CD4081BCN NS Package Number N14A
















Data sheet acquired from Harris Semiconductor SCHS115A – Revised November 1999

The CD4093 types are supplied in a 14-lead hermetic dual-in-line ceramic package (F suffix), 14-lead dual-in-line plastic package (E suffix), 14-lead dual-in-line plastic small-outline package (M), and in chip form (H suffix). Add the suffix 96 to the M package for tape and reel.

PACKAGE THERMAL IMPEDANCE, θJA (See Note 1): E package . . . . . . . . . . . . . . . . . . . . . . . M package . . . . . . . . . . . . . . . . . . . . . . .

NOTE 1:

............................ ............................

80°C/W 86°C/W

Package thermal impedance is calculated in accordance with JESD 51.

VDD

VDD

VOH

VP VN VOL

VSS


PRODUCTION DATA information is current as of publication date. Products conform to specifications per the of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

1

2





3

4


















CD4069UBM/CD4069UBC Inverter Circuits General Description The CD4069UB consists of six inverter circuits and is manufactured using complementary MOS (CMOS) to achieve wide power supply operating range, low power consumption, high noise immunity, and symmetric controlled rise and fall times. This device is intended for all general purpose inverter applications where the special characteristics of the MM74C901, MM74C903, MM74C907, and CD4049A Hex Inverter/Buffers are not required. In those applications requiring larger noise immunity the MM74C14 or MM74C914 Hex Schmitt Trigger is suggested.

All inputs are protected from damage due to static discharge by diode clamps to VDD and VSS.

Features Y Y Y

Y

Wide supply voltage range 3.0V to 15V High noise immunity 0.45 VDD typ. Low power TTL Fan out of 2 driving 74L compatibility or 1 driving 74LS Equivalent to MM54C04/MM74C04

Schematic and Connection Diagram Dual-In-Line Package

TL/F/5975 – 1 TL/F/5975 – 2

Order Number CD4069UB

AC Test Circuits and Switching Time Waveforms

TL/F/5975 – 3 TL/F/5975 – 4


TL/F/5975


CD4069UBM/CD4069UBC Inverter Circuits

February 1988

Absolute Maximum Ratings (Notes 1 & 2)


If Military/Aerospace specified devices are required, please the National Semiconductor Sales Office/Distributors for availability and specifications.

DC Supply Voltage (VDD) Input Voltage (VIN) Operating Temperature Range (TA) CD4069UBM CD4069UBC

b 0.5V to a 18 VDC DC Supply Voltage (VDD) b 0.5V to VDD a 0.5 VDC Input Voltage (VIN) b 65§ C to a 150§ C Storage Temperature Range (TS) Power Dissipation (PD) Dual-In-Line 700 mW Small Outline 500 mW Lead Temperature (TL) (Soldering, 10 seconds) 260§ C

3V to 15VDC 0V to VDD VDC b 55§ C to a 125§ C b 40§ C to a 85§ C

DC Electrical Characteristics CD4069UBM (Note 2) Symbol

Parameter

b 55§ C

Conditions

Min IDD

VOL

VOH

VIL

VIH







lIOl k 1 mA VDD e 5V VDD e 10V VDD e 15V lIOl k 1 mA VDD e 5V VDD e 10V VDD e 15V

Max

a 25§ C

Min

mA

0.5

0.5

15

mA

1.0

1.0

30

mA

0.05 0.05 0.05

0.05 0.05 0.05

V V V

0 0 0 4.95 9.95 14.95

5 10 15

4.0 8.0 12.0

4.0 8.0 12.0

0.64 1.6 4.2

0.51 1.3 3.4 b 0.51 b 1.3 b 3.4

IOH


b 0.64 VDD e 5V, VO e 4.6V b 1.6 VDD e 10V, VO e 9.5V VDD e 15V, VO e 13.5V b4.2

IIN

Input Current


4.95 9.95 14.95 1.0 2.0 3.0

lIOl k 1 mA VDD e 5V, VO e 0.5V VDD e 10V, VO e 1V VDD e 15V, VO e 1.5V VDD e 5V, VO e 0.4V VDD e 10V, VO e 0.5V VDD e 15V, VO e 1.5V

Units

Max 7.5

1.0 2.0 3.0


Min

0.25

4.95 9.95 14.95

IOL

Max

0.25

0.05 0.05 0.05

lIOl k 1 mA VDD e 5V, VO e 4.5V VDD e 10V, VO e 9V VDD e 15V, VO e 13.5V

Typ

a 125§ C

V V V 1.0 2.0 3.0

V V V

4.0 8.0 12.0

V V V

0.88 2.25 8.8

0.36 0.9 2.4

mA mA mA

b 0.88 b 2.25 b 8.8

b 0.36 b 0.9 b 2.4

mA mA mA

b 0.10

b 10 b 5

b 0.10

b 1.0

0.10

10b5

0.10

1.0

mA mA

Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provides conditions for actual device operation. Note 2: VSS e 0V unless otherwise specified. Note 3: IOH and IOL are tested one output at a time.

2

DC Electrical Characteristics CD4069UBC (Note 2) Symbol

Parameter

b 40§ C

Conditions

Min IDD


VOL


VOH


VIL


VIH




Max

a 25§ C

Min

Max

mA

2.0

2.0

15

mA

4.0

4.0

30

mA

0.05 0.05 0.05

0.05 0.05 0.05

V V V

0 0 0 4.95 9.95 14.95

4.95 9.95 14.95 1.0 2.0 3.0


4.0 8.0 12.0

4.0 8.0 12.0

0.52 1.3 3.6

0.44 1.1 3.0 b 0.44 b 1.1 b 3.0



IOH


b 0.52 VDD e 5V, VO e 4.6V b 1.3 VDD e 10V, VO e 9.5V VDD e 15V, VO e 13.5V b3.6

IIN

Input Current


Units

Max 7.5

1.0 2.0 3.0

IOL

Min

1.0

4.95 9.95 14.95


Typ

1.0

0.05 0.05 0.05


a 85§ C

V V V 1.0 2.0 3.0

V V V

4.0 8.0 12.0

V V V

0.88 2.25 8.8

0.36 0.9 2.4

mA mA mA

b 0.88 b 2.25 b 8.8

b 0.36 b 0.9 b 2.4

mA mA mA

b 0.30

b 10 b 5

b 0.30

b 1.0

0.30

10b5

0.30

1.0

mA mA

AC Electrical Characteristics* TA e 25§ C, CL e 50 pF, RL e 200 kX, tr and tf s 20 ns, unless otherwise specified Typ

Max

Units

tPHL or tPLH

Symbol

Propagation Delay Time from Input to Output

Parameter


Conditions

Min

50 30 25

90 60 50

ns ns ns

tTHL or tTLH

Transition Time


80 50 40

150 100 80

ns ns ns

CIN


Any Gate

6

15

pF

D


Any Gate (Note 4)

12

pF

*AC Parameters are guaranteed by DC correlated testing. Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provides conditions for actual device operation. Note 2: VSS e 0V unless otherwise specified. Note 3: IOH and IOL are tested one output at a time. Note 4: D determines the no load AC power consumption of any CMOS device. For complete explanation, see 54C/74C Family Characteristics application noteÐAN-90.

3

Typical Performance Characteristics Gate Transfer Characteristics

Power Dissipation vs Frequency

Propagation Delay vs Ambient Temperature

TL/F/5975 – 6

TL/F/5975–5

TL/F/5975 – 7

Propagation Delay vs Ambient Temperature

Propagation Delay Time vs Load Capacitance

TL/F/5975 – 8

TL/F/5975 – 9

4


Ceramic Dual-In-Line Package (J) Order Number CD4069UBMJ or CD4069UBCJ NS Package Number J14A

5

CD4069UBM/CD4069UBC Inverter Circuits


Molded Dual-In-Line Package (N) Order Number CD4069UBMN or CD4069UBCN NS Package Number N14A








• 1N4099 THRU 1N4135 AVAILABLE IN JANHC AND JANKC PER MIL-PRF-19500/435 • ZENER DIODE CHIPS • ALL JUNCTIONS COMPLETELY PROTECTED WITH SILICON DIOXIDE • 0.5 WATT CAPABILITY WITH PROPER HEAT SINKING • ELECTRICALLY EQUIVALENT TO 1N4099 THRU 1N4135 • COMPATIBLE WITH ALL WIRE BONDING AND DIE ATTACH TECHNIQUES, WITH THE EXCEPTION OF SOLDER REFLOW

CD4099 thru CD4135

23 MILS 15 MILS

MAXIMUM RATINGS

23 MILS

Operating Temperatures: -65°C to +175°C Storage Temperatures: -65°C to +175°C Forward Voltage @ 200 mA: 1.5 Volts maximum

CDI TYPE NUMBER

NOMINAL ZENER VOLTAGE V @I Z ZT

ZENER TEST CURRENT I ZT

(Note 1)

MAXIMUM ZENER IMPEDANCE Z ZT

15 MILS

ELECTRICAL CHARACTERISTICS @ 25°C, unless otherwise speci½ed. MAXIMUM REVERSE LEAKAGE CURRENT I @V R R

(Note 2)

VOLTS

µ A

OHMS

µ A

VOLTS

CD4099 CD4100 CD4101

6.8 7.5 8.2

250 250 250

200 200 200

10.0 10.0 1.0

5.17 5.70 6.24

CD4102 CD4103 CD4104

8.7 9.1 10

250 250 250

200 200 200

1.0 1.0 1.0

6.61 6.92 7.60

CD4105 CD4106 CD4107

11 12 13

250 250 250

200 200 200

.05 .05 .05

8.44 9.12 9.87

CD4108 CD4109 CD4110

14 15 16

250 250 250

200 100 100

.05 .05 .05

10.65 11.40 12.15

CD4111 CD4112 CD4113

17 18 19

250 250 250

100 100 150

.05 .05 .05

12.92 13.67 14.44

CD4114 CD4115 CD4116

20 22 24

250 250 250

150 150 150

.01 .01 .01

15.20 16.72 18.25

AL THICKNESS............25,000 Å Min

CD4117 CD4118 CD4119

25 27 28

250 250 250

150 150 200

.01 .01 .01

19.00 20.46 21.28

GOLD THICKNESS... .....4,000 Å Min

CD4120 CD4121 CD4122

30 33 36

250 250 250

200 200 200

.01 .01 .01

22.80 25.08 27.38

CD4123 CD4124 CD4125

39 43 47

250 250 250

200 250 250

.01 .01 .01

29.65 32.56 35.75

CD4126 CD4127 CD4128

51 56 60

250 250 250

300 300 400

.01 .01 .01

38.76 42.60 45.60

CD4129 CD4130 CD4131

62 68 75

250 250 250

500 700 700

.01 .01 .01

47.10 51.68 57.00

CD4132 CD4133 CD4134 CD4135

82 87 91 100

250 250 250 250

800 1000 1200 1500

.01 .01 .01 .01

62.32 66.12 69.16 76.00

Backside is Cathode

FIGURE 1

DESIGN DATA METALLIZATION: Top: (Anode)........................Al Back:(Cathode)...................Au

CHIP THICKNESS............ ......10 Mils CIRCUIT LAYOUT DATA: For Zener operation, cathode must be operated positive with respect to anode. TOLERANCES: ALL Dimensions + 2 mils

NOTE 1 Zener voltage range equals nominal Zener voltage + 5% for no suffix types. Zener voltage is read using a pulse measurement, 10 milliseconds maximum. "C" suffix = + 2% and "D" suffix = + 1%.

NOTE 2 Zener impedance is derived by superimposing on lZT A 60Hz rms a.c. current equal to 10% of lZT.

6 LAKE STREET, LAWRENCE, PHONE (978) 620-2600 WEBSITE: http://www.microsemi.com

M A S S A C H U S E T T S 01841 FAX (978) 689-0803

189

CD4099

CD4135

thru

1000

500 400 300

3.

3

VO

LT

27

VO

LT

1

100

5. LT

VO

ZENER IMPEDANCE ZZT (OHMS)

200

50 40 30

11

20

VO

LT

10

6.2

VO

LT

5 4 3 2

1 .1

.2 .3 .4 .5

1 2 5 10 20 OPERATING CURRENT lZT (mA)

30 40

50

100

FIGURE 3

ZENER IMPEDANCE VS. OPERATING CURRENT

190

This datasheet has been from: www.datasheetcatalog.com Datasheets for electronics components.

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