Ic 4027 Datasheet 483m64
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INTEGRATED CIRCUITS
DATA SHEET For a complete data sheet, please also : • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC
HEF4027B flip-flops Dual JK flip-flop Product specification File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
HEF4027B flip-flops
Dual JK flip-flop DESCRIPTION
FUNCTION TABLES
The HEF4027B is a dual JK flip-flop which is edge-triggered and features independent set direct (SD), clear direct (CD), clock () inputs and outputs (O,O). Data is accepted when is LOW, and transferred to the output on the positive-going edge of the clock. The active HIGH asynchronous clear-direct (CD) and set-direct (SD) are independent and override the J, K, and inputs. The outputs are buffered for best system performance. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.
INPUTS
OUTPUTS
SD
CD
J
K
O
O
H
L
X
X
X
H
L
L
H
X
X
X
L
H
H
H
X
X
X
H
H
INPUTS SD
CD
L
OUTPUTS J
K
On + 1
On + 1
L
L
L
L
L
H
L
H
L
L
L
L
H
L
H
L
L
H
H
On
On
no change
Notes 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial = positive-going transition On + 1 = state after clock positive transition PINNING
Fig.1 Functional diagram.
J,K
synchronous inputs
clock input (L to H edge-triggered)
SD
asynchronous set-direct input (active HIGH)
CD
asynchronous clear-direct input (active HIGH)
O
true output
O
complement output
HEF4027BP(N):
16-lead DIL; plastic (SOT38-1)
HEF4027BD(F):
16-lead DIL; ceramic (cerdip) (SOT74)
HEF4027BT(D):
16-lead SO; plastic (SOT109-1)
( ): Package Designator North America FAMILY DATA, IDD LIMITS category FLIP-FLOPS See Family Specifications
Fig.2 Pinning diagram.
January 1995
2
Philips Semiconductors
Product specification
HEF4027B flip-flops
Dual JK flip-flop
Fig.3 Logic diagram (one flip-flop).
AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V
SYMBOL
MIN.
TYP.
MAX.
TYPICAL EXTRAPOLATION FORMULA
Propagation delays → O, O HIGH to LOW
5 10
tPHL
15 5 LOW to HIGH
10
tPLH
15 SD → O LOW to HIGH
HIGH to LOW SD → O HIGH to LOW
78 ns + (0,55 ns/pF) CL
80 ns
29 ns + (0,23 ns/pF) CL
30
60 ns
22 ns + (0,16 ns/pF) CL
85
170 ns
58 ns + (0,55 ns/pF) CL
35
70 ns
27 ns + (0,23 ns/pF) CL
30
60 ns
22 ns + (0,16 ns/pF) CL
70
140 ns
43 ns + (0,55 ns/pF) CL
60 ns
19 ns + (0,23 ns/pF) CL
25
50 ns
17 ns + (0,16 ns/pF) CL
120
240 ns
93 ns + (0,55 ns/pF) CL
45
90 ns
33 ns + (0,23 ns/pF) CL
15
35
70 ns
27 ns + (0,16 ns/pF) CL
5
140
280 ns
113 ns + (0,55 ns/pF) CL
55
110 ns
44 ns + (0,23 ns/pF) CL
40
80 ns
32 ns + (0,16 ns/pF) CL
tPLH
5 10
10
tPHL
tPHL
15
January 1995
210 ns
40
30
5 10 15
CD → O
105
3
Philips Semiconductors
Product specification
HEF4027B flip-flops
Dual JK flip-flop
VDD V CD → O LOW to HIGH Output transition times HIGH to LOW
LOW to HIGH
SYMBOL
MIN.
TYP.
5
75
J,K → Hold time J,K → Minimum clock pulse width; LOW Minimum SD, CD pulse width; HIGH
for SD, CD
35
70 ns
24 ns + (0,23 ns/pF) CL
50 ns
17 ns + (0,16 ns/pF) CL
5
60
120 ns
tPLH
(1,0 ns/pF) CL
30
60 ns
9 ns + (0,42 ns/pF) CL
20
40 ns
6 ns + (0,28 ns/pF) CL
5
60
120 ns
30
60 ns
9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL
10
10
tTHL
tTLH
20
40 ns
50
25
ns
30
10
ns
15
20
5
ns
5
25
0
ns
20
0
ns
5 10
10
tsu
thold
15
15
5
ns
5
80
40
ns
30
15
ns
15
24
12
ns
5
90
45
ns
40
20
ns
30
15
ns
20
ns
tRSD, tRCD
−15
15
−10
ns
10
−5
ns
4
8
MHz
fmax
12
25
MHz
15
30
MHz
10
10
tWL
tWSDH, tWCDH
5 10 5
pulse frequency
10
J = K = HIGH
15
VDD V Dynamic power
10 ns +
15
15 Maximum clock
48 ns + (0,55 ns/pF) CL
25
10
15 Recovery time
150 ns
15
15 Set-up time
TYPICAL EXTRAPOLATION FORMULA
MAX.
5
10 ns +
(1,0 ns/pF) CL
see also waveforms Figs 4 and 5
see also waveforms Fig.4
TYPICAL FORMULA FOR P (µW) 900 fi + ∑ (foCL) × VDD2
dissipation per
10
4 500 fi + ∑ (foCL) ×
package (P)
15
13 200 fi + ∑ (foCL) ×
VDD2 VDD2
where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V)
January 1995
4
Philips Semiconductors
Product specification
HEF4027B flip-flops
Dual JK flip-flop
Fig.4
Waveforms showing set-up times, hold times and minimum clock pulse width. Set-up and hold times are shown as positive values but may be specified as negative values.
Fig.5 Waveforms showing recovery times for SD and CD; minimum SD and CD pulse widths.
APPLICATION INFORMATION Some examples of applications for the HEF4027B are: • s • Counters • Control circuits January 1995
5
DATA SHEET For a complete data sheet, please also : • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC
HEF4027B flip-flops Dual JK flip-flop Product specification File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
HEF4027B flip-flops
Dual JK flip-flop DESCRIPTION
FUNCTION TABLES
The HEF4027B is a dual JK flip-flop which is edge-triggered and features independent set direct (SD), clear direct (CD), clock () inputs and outputs (O,O). Data is accepted when is LOW, and transferred to the output on the positive-going edge of the clock. The active HIGH asynchronous clear-direct (CD) and set-direct (SD) are independent and override the J, K, and inputs. The outputs are buffered for best system performance. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.
INPUTS
OUTPUTS
SD
CD
J
K
O
O
H
L
X
X
X
H
L
L
H
X
X
X
L
H
H
H
X
X
X
H
H
INPUTS SD
CD
L
OUTPUTS J
K
On + 1
On + 1
L
L
L
L
L
H
L
H
L
L
L
L
H
L
H
L
L
H
H
On
On
no change
Notes 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial = positive-going transition On + 1 = state after clock positive transition PINNING
Fig.1 Functional diagram.
J,K
synchronous inputs
clock input (L to H edge-triggered)
SD
asynchronous set-direct input (active HIGH)
CD
asynchronous clear-direct input (active HIGH)
O
true output
O
complement output
HEF4027BP(N):
16-lead DIL; plastic (SOT38-1)
HEF4027BD(F):
16-lead DIL; ceramic (cerdip) (SOT74)
HEF4027BT(D):
16-lead SO; plastic (SOT109-1)
( ): Package Designator North America FAMILY DATA, IDD LIMITS category FLIP-FLOPS See Family Specifications
Fig.2 Pinning diagram.
January 1995
2
Philips Semiconductors
Product specification
HEF4027B flip-flops
Dual JK flip-flop
Fig.3 Logic diagram (one flip-flop).
AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V
SYMBOL
MIN.
TYP.
MAX.
TYPICAL EXTRAPOLATION FORMULA
Propagation delays → O, O HIGH to LOW
5 10
tPHL
15 5 LOW to HIGH
10
tPLH
15 SD → O LOW to HIGH
HIGH to LOW SD → O HIGH to LOW
78 ns + (0,55 ns/pF) CL
80 ns
29 ns + (0,23 ns/pF) CL
30
60 ns
22 ns + (0,16 ns/pF) CL
85
170 ns
58 ns + (0,55 ns/pF) CL
35
70 ns
27 ns + (0,23 ns/pF) CL
30
60 ns
22 ns + (0,16 ns/pF) CL
70
140 ns
43 ns + (0,55 ns/pF) CL
60 ns
19 ns + (0,23 ns/pF) CL
25
50 ns
17 ns + (0,16 ns/pF) CL
120
240 ns
93 ns + (0,55 ns/pF) CL
45
90 ns
33 ns + (0,23 ns/pF) CL
15
35
70 ns
27 ns + (0,16 ns/pF) CL
5
140
280 ns
113 ns + (0,55 ns/pF) CL
55
110 ns
44 ns + (0,23 ns/pF) CL
40
80 ns
32 ns + (0,16 ns/pF) CL
tPLH
5 10
10
tPHL
tPHL
15
January 1995
210 ns
40
30
5 10 15
CD → O
105
3
Philips Semiconductors
Product specification
HEF4027B flip-flops
Dual JK flip-flop
VDD V CD → O LOW to HIGH Output transition times HIGH to LOW
LOW to HIGH
SYMBOL
MIN.
TYP.
5
75
J,K → Hold time J,K → Minimum clock pulse width; LOW Minimum SD, CD pulse width; HIGH
for SD, CD
35
70 ns
24 ns + (0,23 ns/pF) CL
50 ns
17 ns + (0,16 ns/pF) CL
5
60
120 ns
tPLH
(1,0 ns/pF) CL
30
60 ns
9 ns + (0,42 ns/pF) CL
20
40 ns
6 ns + (0,28 ns/pF) CL
5
60
120 ns
30
60 ns
9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL
10
10
tTHL
tTLH
20
40 ns
50
25
ns
30
10
ns
15
20
5
ns
5
25
0
ns
20
0
ns
5 10
10
tsu
thold
15
15
5
ns
5
80
40
ns
30
15
ns
15
24
12
ns
5
90
45
ns
40
20
ns
30
15
ns
20
ns
tRSD, tRCD
−15
15
−10
ns
10
−5
ns
4
8
MHz
fmax
12
25
MHz
15
30
MHz
10
10
tWL
tWSDH, tWCDH
5 10 5
pulse frequency
10
J = K = HIGH
15
VDD V Dynamic power
10 ns +
15
15 Maximum clock
48 ns + (0,55 ns/pF) CL
25
10
15 Recovery time
150 ns
15
15 Set-up time
TYPICAL EXTRAPOLATION FORMULA
MAX.
5
10 ns +
(1,0 ns/pF) CL
see also waveforms Figs 4 and 5
see also waveforms Fig.4
TYPICAL FORMULA FOR P (µW) 900 fi + ∑ (foCL) × VDD2
dissipation per
10
4 500 fi + ∑ (foCL) ×
package (P)
15
13 200 fi + ∑ (foCL) ×
VDD2 VDD2
where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V)
January 1995
4
Philips Semiconductors
Product specification
HEF4027B flip-flops
Dual JK flip-flop
Fig.4
Waveforms showing set-up times, hold times and minimum clock pulse width. Set-up and hold times are shown as positive values but may be specified as negative values.
Fig.5 Waveforms showing recovery times for SD and CD; minimum SD and CD pulse widths.
APPLICATION INFORMATION Some examples of applications for the HEF4027B are: • s • Counters • Control circuits January 1995
5
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