Interfacing 6m3j2b
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Microprocessors/6th/EcE/Dipankar Mishra
April 1, 2011
I/O Interfacing Chips 8212 : I/O Interfacing Chip It is a 24 pin IC which provides ports of terminals for interfacing of Input and output devices with the 8085 microprocessor. It consists of 8 D type latches. These latches provide temporary storage of data when data transfer takes place between I/O Devices and 8085 microprocessor. These devices are also known as buffers. It has 8 input lines identified as DI1 to DI8 and 8 output lines identified as DO1 to DO8. When it is used to communicate or transfer data from input devices, input lines are used while output lines are used for data transfer to output devices. Two selecting lines DS1 and DS2 are used to identify what device will be interfaced along with a control signal MD. MD = 1 DS 1 = 0 DS 2 = 1 is the state when 8212 selects the output device. MD = 0 DS 1 = 0 DS 2 = 1 is the state when 8212 selects the input device.
Steps of data transfer Microprocessor to Output Device • • • •
The processor will load the data to the port. The port will send a message to the output device to read the data. The output device will read the data from the port. After the data have been read by the output device the processor can load the next data to the port.
Input Device to Microprocessor • • • •
The input device will load the data to the port. When the port receives a data, it sends message to the processor to read the data. The processor will read the data from the port. After a data have been read by the processor the input device will load the next data into the port.
8155 : Peripheral Interface Chip It Consists of
Microprocessors/6th/EcE/Dipankar Mishra • • • • • • •
April 1, 2011
256 bytes of RAM 2 programmable I/O ports A and B 5 bit parallel port C 14 bit Timer operating in 4 different modes Six internal addresses Chip select signal CS which is active low 8 address lines and 5 control lines
Internal Address of 8155
8255 : Programmable Peripheral Interface
Internal Block Diagram of 8255 The Intel 8255 is a general purpose programmable I/O device which is designed for use with all Intel and most other microprocessors. It provides 24
Microprocessors/6th/EcE/Dipankar Mishra
April 1, 2011
I/O pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation. In MODE 0, each group of 12 I/O pins may be programmed in sets of 4 and 8 to be inputs or outputs. In MODE 1, each group may be programmed to have 8 lines of input or output. 3 of the remaining 4 pins are used for handshaking and interrupt control signals. MODE 2 is a strobed bi-directional bus configuration. Two control groups, labeled group A control and group B control define how the three I/O ports operate. There are several different operating modes for the 8255 and these modes must be defined by the U writing programming or control words to the device 8255. The line group of port C consists of two 4 bit ports. One of the 4 bit group is associated with group A control and the other 4 bit group with group B control device signals. The upper 4 bits of port C are associated with group A control while the lower 4 bits are associated with group B control. The final logic blocks are read/write control logic and data bus buffer. These blocks provide the electrical interface between the 8085 and the 8255. The data bus buffer buffers the data I/O lines to/from the 8085 data bus. The read/write control logic routes the data to and from the correct internal s with the right timing. The internal path being enabled depends on the type of operation performed by the 8085. The type of operation can be I/O read or I/O write.
8259 : Programmable Interrupt Controller The 8259 PIC controls the U's interrupt mechanism, by accepting several interrupt requests and feeding them to the processor in order. For instance, when a keyboard s a key-hit, it sends a pulse along it's interrupt line (IRQ 1) to the PIC chip, which then translates the IRQ into a system interrupt, and sends a message to interrupt the U from whatever it is doing. Part of the kernel's job is to either handle these IRQs and perform the necessary procedures (poll the keyboard for the scan code) or alert a space program to the interrupt (send a message to the keyboard driver). Without a PIC, you would have to poll or continuously monitor all the devices in the system to see if they want to do anything (signal an event), but with a PIC, your system can run along nicely until such time that a device wants to signal an event, which means you don't waste time going to the devices, you let the devices come to you when they are ready.
Microprocessors/6th/EcE/Dipankar Mishra
April 1, 2011
8259 connected to 8085 8259 Features •
• • • •
Has 8 external Interrupt requests with priority level 0 – 7. In other words it provides handling of 8 independent interrupts which can be extended to 63 by cascading. Each request is separately maskable. Normal priority IRQ0 is highest and IRQ7 lowest. Each request is treated at a separate level. Operates in two modes : Real Mode and Protected mode
Block Diagram
Block Diagram of 8259
Microprocessors/6th/EcE/Dipankar Mishra
April 1, 2011
8279 : Programmable keyboard/ Display Controller The INTEL 8279 is specially developed for interfacing keyboard and display devices to 8085/8086/8088 microprocessor based system. The important features of 8279 are,
Functional Block Diagram of 8279 Features o o o o o
Simultaneous keyboard and display operations. Scanned keyboard mode. Scanned sensor mode. 8-character keyboard FIFO. 1 66-character display.
Keyboard section:
• •
The keyboard section consists consists of eight return lines RL0 - RL7 that can be used to form the columns of a keyboard matrix. It has two additional input : shift and control/strobe. The keys are automatically debounced.
Microprocessors/6th/EcE/Dipankar Mishra • • • • •
April 1, 2011
The two operating modes of keyboard section are 22-key lockout and Nkey rollover. In the 22-key lockout mode, if two keys are pressed simultaneously, only the first key is recognized. In the NN-key rollover mode simultaneous keys are recognized and their codes are stored in FIFO. The keyboard section also have an 8 x 8 FIFO (First In First Out) RAM. The FIFO can store eight key codes in the scan keyboard mode. The status of the shift key and control key are also stored along with key code. The 8279 generate an interrupt signal when there is an entry in FIFO. The format of key code entry in FIFO for scan keyboard mode is,
In sensor matrix mode the condition (i.e., open/close status) of 64 switches is stored in FIFO RAM. If the condition of any of the switches changes then the 8279 asserts IRQ as high to interrupt the processor. processor. Display section:
• •
• • • •
The display section has eight eight output lines divided into two groups A0A0A3 and B0B0-B3. The output lines can be used either as a single group of eight lines or as two groups of four lines, in conjunction with the scan lines for a multiplexed display. The output lines are connected to the the anodes through driver transistor in case of common cathode 77-segment LEDs. The cathodes are connected to scan lines through driver transistors. The display can be blanked by BD (low) line. The display section consists of 16 x 8 display RAM. The U can read from or write into any location of the display RAM.
Scan section:
• • •
The scan section has a scan counter and four scan lines, SL0 to SL3. In decoded scan mode, the output of scan lines will be similar to a 22-toto4 decoder. In encoded scan mode, the output output of scan lines will be binary count, and so an external decoder should be used to convert the binary count to decoded output.
Microprocessors/6th/EcE/Dipankar Mishra • •
April 1, 2011
The scan lines are common for keyboard and display. The scan lines are used to form the rows of a matrix keyboard and also connected connected to digit drivers of a multiplexed display, to turn ON/OFF.
U interface section:
• • • • • • •
The U interface section takes care of data transfer between 8279 and the processor. This section has eight bidirectional data lines DB0 to DB7 for data transfer between 8279 and U. It requires two internal address A =0 for selecting data buffer and A = 1 for selecting control of8279. The control signals WR (low), RD (low), CS (low) (low) and A0 are used for read/write to 8279. It has an interrupt request line IRQ, for interrupt driven data transfer with processor. The 8279 require an internal clock frequency of 100 kHz. This can be obtained by dividing the input clock by an internal prescaler. prescaler. The RESET signal sets the 8279 in 1616-character display with two -key lockout keyboard modes.
Programming the 8279:
•
The 8279 can be programmed to perform various functions through eight command words.
8254 : Programmable Interval Timer
Microprocessors/6th/EcE/Dipankar Mishra
April 1, 2011
Features 1. Three independent 16-bit down counters. 2) 8254 can handle inputs from DC to 10 MHz 3. Three counters are identical presettable, and can be programmed for either binary or BCD count. 4) Counter can be programmed in six different modes. 5) Compatible with all Intel and most other microprocessors. 6) 8254 has powerful command called READ BACK command which allows the to check the count value, programmed mode and current mode and current status of the counter. Data Bus Buffer : This tri-state, bi-directional, 8-bit buffer is used to interface the 8253/54 to the system data bus. The Data bus buffer has three basic functions. 1. Programming the modes of 8253/54. 2. Loading the count s. 3. Reading the count values. Read/Write Logic : The Read/Write logic has five signals : RD, WR, CS and the address lines A0 and A1. In the peripheral I/O mode, the RD, and WR signals are connected to IOR and IOW, respectively. In memory-mapped I/O, these are connected to MEMR and MEMW. Address lines A0 and A1 of the U are usually connected to lines A0 and A1 of the 8253/54, and CS is tied to a decoded address. The control word and counters are selected according to the signals on lines A0 and A1.
Control Word : This is accessed when lines A0 and A1 are at logic 1. It is used to write a command word which specifies the counter to be used (binary or BCD), its mode, and either a read or write operation. Counters : These three functional blocks are identical in operation. Each counter consists of a single, 16 bit, pre-settable, down counter. The counter can operate in either binary or BCD and its input, gate and output are configured by the selection of modes stored in the control word . The counters are fully independent. 8254 programming
Microprocessors/6th/EcE/Dipankar Mishra
April 1, 2011
April 1, 2011
I/O Interfacing Chips 8212 : I/O Interfacing Chip It is a 24 pin IC which provides ports of terminals for interfacing of Input and output devices with the 8085 microprocessor. It consists of 8 D type latches. These latches provide temporary storage of data when data transfer takes place between I/O Devices and 8085 microprocessor. These devices are also known as buffers. It has 8 input lines identified as DI1 to DI8 and 8 output lines identified as DO1 to DO8. When it is used to communicate or transfer data from input devices, input lines are used while output lines are used for data transfer to output devices. Two selecting lines DS1 and DS2 are used to identify what device will be interfaced along with a control signal MD. MD = 1 DS 1 = 0 DS 2 = 1 is the state when 8212 selects the output device. MD = 0 DS 1 = 0 DS 2 = 1 is the state when 8212 selects the input device.
Steps of data transfer Microprocessor to Output Device • • • •
The processor will load the data to the port. The port will send a message to the output device to read the data. The output device will read the data from the port. After the data have been read by the output device the processor can load the next data to the port.
Input Device to Microprocessor • • • •
The input device will load the data to the port. When the port receives a data, it sends message to the processor to read the data. The processor will read the data from the port. After a data have been read by the processor the input device will load the next data into the port.
8155 : Peripheral Interface Chip It Consists of
Microprocessors/6th/EcE/Dipankar Mishra • • • • • • •
April 1, 2011
256 bytes of RAM 2 programmable I/O ports A and B 5 bit parallel port C 14 bit Timer operating in 4 different modes Six internal addresses Chip select signal CS which is active low 8 address lines and 5 control lines
Internal Address of 8155
8255 : Programmable Peripheral Interface
Internal Block Diagram of 8255 The Intel 8255 is a general purpose programmable I/O device which is designed for use with all Intel and most other microprocessors. It provides 24
Microprocessors/6th/EcE/Dipankar Mishra
April 1, 2011
I/O pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation. In MODE 0, each group of 12 I/O pins may be programmed in sets of 4 and 8 to be inputs or outputs. In MODE 1, each group may be programmed to have 8 lines of input or output. 3 of the remaining 4 pins are used for handshaking and interrupt control signals. MODE 2 is a strobed bi-directional bus configuration. Two control groups, labeled group A control and group B control define how the three I/O ports operate. There are several different operating modes for the 8255 and these modes must be defined by the U writing programming or control words to the device 8255. The line group of port C consists of two 4 bit ports. One of the 4 bit group is associated with group A control and the other 4 bit group with group B control device signals. The upper 4 bits of port C are associated with group A control while the lower 4 bits are associated with group B control. The final logic blocks are read/write control logic and data bus buffer. These blocks provide the electrical interface between the 8085 and the 8255. The data bus buffer buffers the data I/O lines to/from the 8085 data bus. The read/write control logic routes the data to and from the correct internal s with the right timing. The internal path being enabled depends on the type of operation performed by the 8085. The type of operation can be I/O read or I/O write.
8259 : Programmable Interrupt Controller The 8259 PIC controls the U's interrupt mechanism, by accepting several interrupt requests and feeding them to the processor in order. For instance, when a keyboard s a key-hit, it sends a pulse along it's interrupt line (IRQ 1) to the PIC chip, which then translates the IRQ into a system interrupt, and sends a message to interrupt the U from whatever it is doing. Part of the kernel's job is to either handle these IRQs and perform the necessary procedures (poll the keyboard for the scan code) or alert a space program to the interrupt (send a message to the keyboard driver). Without a PIC, you would have to poll or continuously monitor all the devices in the system to see if they want to do anything (signal an event), but with a PIC, your system can run along nicely until such time that a device wants to signal an event, which means you don't waste time going to the devices, you let the devices come to you when they are ready.
Microprocessors/6th/EcE/Dipankar Mishra
April 1, 2011
8259 connected to 8085 8259 Features •
• • • •
Has 8 external Interrupt requests with priority level 0 – 7. In other words it provides handling of 8 independent interrupts which can be extended to 63 by cascading. Each request is separately maskable. Normal priority IRQ0 is highest and IRQ7 lowest. Each request is treated at a separate level. Operates in two modes : Real Mode and Protected mode
Block Diagram
Block Diagram of 8259
Microprocessors/6th/EcE/Dipankar Mishra
April 1, 2011
8279 : Programmable keyboard/ Display Controller The INTEL 8279 is specially developed for interfacing keyboard and display devices to 8085/8086/8088 microprocessor based system. The important features of 8279 are,
Functional Block Diagram of 8279 Features o o o o o
Simultaneous keyboard and display operations. Scanned keyboard mode. Scanned sensor mode. 8-character keyboard FIFO. 1 66-character display.
Keyboard section:
• •
The keyboard section consists consists of eight return lines RL0 - RL7 that can be used to form the columns of a keyboard matrix. It has two additional input : shift and control/strobe. The keys are automatically debounced.
Microprocessors/6th/EcE/Dipankar Mishra • • • • •
April 1, 2011
The two operating modes of keyboard section are 22-key lockout and Nkey rollover. In the 22-key lockout mode, if two keys are pressed simultaneously, only the first key is recognized. In the NN-key rollover mode simultaneous keys are recognized and their codes are stored in FIFO. The keyboard section also have an 8 x 8 FIFO (First In First Out) RAM. The FIFO can store eight key codes in the scan keyboard mode. The status of the shift key and control key are also stored along with key code. The 8279 generate an interrupt signal when there is an entry in FIFO. The format of key code entry in FIFO for scan keyboard mode is,
In sensor matrix mode the condition (i.e., open/close status) of 64 switches is stored in FIFO RAM. If the condition of any of the switches changes then the 8279 asserts IRQ as high to interrupt the processor. processor. Display section:
• •
• • • •
The display section has eight eight output lines divided into two groups A0A0A3 and B0B0-B3. The output lines can be used either as a single group of eight lines or as two groups of four lines, in conjunction with the scan lines for a multiplexed display. The output lines are connected to the the anodes through driver transistor in case of common cathode 77-segment LEDs. The cathodes are connected to scan lines through driver transistors. The display can be blanked by BD (low) line. The display section consists of 16 x 8 display RAM. The U can read from or write into any location of the display RAM.
Scan section:
• • •
The scan section has a scan counter and four scan lines, SL0 to SL3. In decoded scan mode, the output of scan lines will be similar to a 22-toto4 decoder. In encoded scan mode, the output output of scan lines will be binary count, and so an external decoder should be used to convert the binary count to decoded output.
Microprocessors/6th/EcE/Dipankar Mishra • •
April 1, 2011
The scan lines are common for keyboard and display. The scan lines are used to form the rows of a matrix keyboard and also connected connected to digit drivers of a multiplexed display, to turn ON/OFF.
U interface section:
• • • • • • •
The U interface section takes care of data transfer between 8279 and the processor. This section has eight bidirectional data lines DB0 to DB7 for data transfer between 8279 and U. It requires two internal address A =0 for selecting data buffer and A = 1 for selecting control of8279. The control signals WR (low), RD (low), CS (low) (low) and A0 are used for read/write to 8279. It has an interrupt request line IRQ, for interrupt driven data transfer with processor. The 8279 require an internal clock frequency of 100 kHz. This can be obtained by dividing the input clock by an internal prescaler. prescaler. The RESET signal sets the 8279 in 1616-character display with two -key lockout keyboard modes.
Programming the 8279:
•
The 8279 can be programmed to perform various functions through eight command words.
8254 : Programmable Interval Timer
Microprocessors/6th/EcE/Dipankar Mishra
April 1, 2011
Features 1. Three independent 16-bit down counters. 2) 8254 can handle inputs from DC to 10 MHz 3. Three counters are identical presettable, and can be programmed for either binary or BCD count. 4) Counter can be programmed in six different modes. 5) Compatible with all Intel and most other microprocessors. 6) 8254 has powerful command called READ BACK command which allows the to check the count value, programmed mode and current mode and current status of the counter. Data Bus Buffer : This tri-state, bi-directional, 8-bit buffer is used to interface the 8253/54 to the system data bus. The Data bus buffer has three basic functions. 1. Programming the modes of 8253/54. 2. Loading the count s. 3. Reading the count values. Read/Write Logic : The Read/Write logic has five signals : RD, WR, CS and the address lines A0 and A1. In the peripheral I/O mode, the RD, and WR signals are connected to IOR and IOW, respectively. In memory-mapped I/O, these are connected to MEMR and MEMW. Address lines A0 and A1 of the U are usually connected to lines A0 and A1 of the 8253/54, and CS is tied to a decoded address. The control word and counters are selected according to the signals on lines A0 and A1.
Control Word : This is accessed when lines A0 and A1 are at logic 1. It is used to write a command word which specifies the counter to be used (binary or BCD), its mode, and either a read or write operation. Counters : These three functional blocks are identical in operation. Each counter consists of a single, 16 bit, pre-settable, down counter. The counter can operate in either binary or BCD and its input, gate and output are configured by the selection of modes stored in the control word . The counters are fully independent. 8254 programming
Microprocessors/6th/EcE/Dipankar Mishra
April 1, 2011
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