Sense Amplifiers For Sram 4p154a

Sense Amplifiers for SRAMs

Details of registration Name

Mudasir Bashir

Roll No.714025 Supervisor Dr. PATRI SRIHARI RAO Date of 18-July 2014 registration Type of Full-time registration No. of semesters 01 completed

Presentation Outline: • Course Work • Motivation • SRAMs • Sense Amplifier – Classification •Bit-line model •Literature Survey •Design Issues •Proposed Work •Future Work •References

Course Work: S.No

Subjects

Credits

Type

Semester

1.

Analog IC Design

4

Class Work

Ist Sem

2.

Device Modelling

3

Class Work

Ist Sem

3.

English for Scientific Communication

Audit

Class Work

Ist Sem

Motivation •

According to the 2002 ITRS, the memory chip will occupy 90% of the chip area by 2013.

•

SRAM is widely used to store digital data

•

Highly compatible to standard CMOS processes

•

Major Issues: — Charge retention — Endurance — Scaling

•

Sense amplifiers are one of the important peripheral devices in SRAMs.

6T SRAM Cell – Cell size s for most of array size • Reduce cell size at expense of complexity – 6T SRAM Cell • Used in most commercial chips • Data stored in cross-coupled inverters – Read: • Precharge bit, bit_b

bit

word

• Raise wordline – Write: • Drive data onto bit, bit_b • Raise wordline

Source [9]

bit_b

Sense Amplifiers •

Active circuits

•

Used to retrieve the stored data in the memory cell

•

Reduces the access time

•

Amplify the signal variations on the bit line

output small transition

input s.a.

Sensing Amplifier Design Objective and Classification • Design Objective – Minimum sense delay – Required amplification – Minimum power consumption – Restricted layout area – Highly reliable 

Minimum Sense Dead Zones

• Classification

Circuit Types

Opération Mode

Differential

Voltage-mode

Non-differential

Current-mode

Methods of Sensing

Source: [10]

Bit Line Model

Source [1]

Delay for Voltage-Mode

[Evert Seevinck et.al]

RC delay

For voltage-mode signals, RL is infinite and the output signal is the open-circuit voltage Vo .

Delay for Current-Mode For current-mode signals, RL is ideally zero and the output signal is the short-circuit current Io.

Example • When – RB = 2500Ω – RT=250Ω – CT=2pf • Voltage-mode – δtv = 5.25ns • Current-mode – δti = 0.235ns

Paper Name

Topology Proposed

Pros

Cons

Modification

Macro.et.al, "Analog S/A for high density NOR flash memories”, IEEE, 1992

Two Voltage mode S/A, 1 CMSA, Performance comparison

Low area Data retention, overhead, Current conveyer CMSA better performance, CMSA can be made llel & more than one cells can be accessed

Consideration of mismatch effects

Daejin Park. et.al, "Built in binary code inversion technique for on chip S/A”, IEEE, 2014 Y.Tsiatouches et.al, "New memory S/A design in CMOS technology”, IEEE, 2007

3 Inversion schemes introduced, Clamped bit line S/A

Reduced the Computational sensing current of overhead, S/A Large no. of gate counts, Access delay

Current sensing approach, Proposed two topologies:-CMS & CCS

Small voltage Current conveyer, Accuracy, swing on the Sense Access time Access time bitlines, CMS has better performance than CCS, area

---------

Otsuk et.al, "Circuit techniques for 1.5V power supply flash memory”, IEEE, 2001

Self biasing, Clamped bit line S/A, N channel transistor

Low power operation

Use of dummy Current mirror bitline for every SA. Need of nchannel transistor

A conte et.al, "A Folded mirror 1.35V S/A for non active load volatile memories based on CM applications ”, IEEE 2004

Gain is increased by factor 2, Improves slew rate, Speed up the precharge phase

Area

Ali Hajimiri et.al, "Design issues in cross coupled inverters S/A”, IEEE,2009

Fast sensing operation

Mismatch effects, Accuracy, Current conveyer Mismatch effects

+ve is exploited in CMOS cross coupled inverter pair S/A

------------

Literature Survey (cont’d): A. Chrisanthopoulo et.al, “Comparative study of different current mode sense amplifiers in submicron CMOS technology”, IEEE Proc. Circuits Devices Syst., Vol. 149, No. 3, June 2002 . B. Siti Lailatul Mohd et.al, “Comparative study on 8T SRAM with different types of sense amplifiers” IEEE-ICSE 2014 Proc. 2014.

Cont’d..

Sense Amplifier Design Issues: • Most of the CMSA configurations use current conveyer for Precharging

VBL =VBL’

• Sense dead zones • Bit-line leakage • Mismatch effects : – Threshold mismatch – Transconductance mismatch

Source [7]

Proposed Work: • Modification of Clamped Bit-line CSA by replacing the current conveyer circuits for accurate results. • Optimization of design issues

Proposed CSA

V01

V02

Simulations:

Transient response of CSA during read operation

Simulations (cont’d):

Power Dissipation VS Temperature

Variation of Sense Delay w.r.t. Bitline Capacitance

Comparison table: This work

[11]

180 nm

180 nm

Input Differential Current (µA)

98

80

Frequency (MHz)

500

500

Power Supply (V)

1.8

1.8

Sense Delay (pS)

596.6 (764)

723

~ 88

-------

CMOS Technology

Power Consumption (uW)

Layout

Extracted view

Future Work: •

Complete my course work

•

Sense Dead zones

•

Mismatch & bitline leakage effects

•

New Analog/Mixed signal design layout strategies

•

ADC’s Memory section (SRAM +SA)

ADC

Proposed work flow

Analog application like Image Sensors, Touch screens, pace maker

References: [1] E. Sccvinck, P. J. van Beers, and H. Ontrop, “Current-Mode Techniques for High- Speed VLSI Circuits with Application to Current Sense Amplifier for CMOS SRAMs,” IEEE Journal of Solid-State Circuits Vol.26 No.4 pp.525-536 April 1991. [2] T. P. Haraszti, “High Performance CMOS Sense Amplifiers,” United States Patent No. 4,169, 233, Sep. 1979. [3] Tegze P. Haraszti, “CMOS Memory Circuits”, Kluwer Academic Publishers, 2000. [4] V.Kristovski and Y. L. Pogrbeny, “New Sense Amplifier for Small-Swing CMOS Logic Circuit,” IEEE Trans, On Circuit and Systems, vol. 47, p.p. 573~576, June 2000. [5] Evert Seevinck, Petrus J. van Beers, Hans Ontrop, “Current mode techniques for high speed VLSI circuits with the application of CSMA for CMOS SRAMs”, IEEE JOURNAL OF SOLIDSTATE CIRCUITS, Vol. 26, No. 4, April 1991. [6] Do Anh-Tuan et. Al, “Hybrid-Mode SRAM Sense Amplifiers: New Approach on Transistor Sizing”, IEEE Transactions On Circuits And Systems—ii: Express Briefs, Vol. 55, No. 10, October 2008

References: [7] A. Chrisanthopoulo et.al, “Comparative study of different current mode sense amplifiers in submicron CMOS technology”, IEEE Proc. Circuits Deuices Syst., Vol. 149, No. 3, June 2002 . [8] ROBERTO BEZ et.al, “Introduction to Flash Memory”, Proceedings of the IEEE, Vol. 91, No. 4, April 2003. [9] Majumdar, B et. Al, “Low power single bitline 6T SRAM cell with high read stability”, International Conference on Recent Trends in Information Systems (ReTIS), 2011. [10] B. Wicht, "Current Sense Amplifiers for Embedded SRAM in High Performance System on a Chip Designs", Springer,1st edition ,2003. [11] S. Patil, M. Wieckowski, and M. Margala, “A self-biased charge transfer sense amplifier,” in IEEE Int. Symp. Circuits Syst., vol. 4, pp. 3030–3033, 2007.

THANKS!!!