Zam70 La-a901p R03 Dell Latitude E5450 6y241l

A

B

C

D

E

COMPAL CONFIDENTIAL MODEL NAME : ZAM70 DAA0007U000 PCB NO : BOM P/N : 4319R031L01 (SMT MB AA901 ZAM70 U W/DOCK I5 1.9G R1)

1

1

4319R031L02 (SMT MB AA901 ZAM70 U W/DOCK I3 1.9G R1)

GPIO MAP: 3.6C

Huston 14" UMA

2

2

Broadwell U

2014-03-07

REV : 0.3 (X01) @ : Nopop Component EMC@ : EMI, ESD and RF Component @EMC@ : EMI, ESD and RF Nopop Component CXDP@ : XDP Component VPRO@ : VPRO CONN@ : Connector Component

3

U1@ UC1

U_QG22

U2@ UC1

3

U3@ UC1

U_QG21

U_QG5M

MB PCB Part Number

Description

DAA0007U000

PCB 13D LA-A901P REV0 MB/UMA DOCK 1

Layout Dell logo

4

4

DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.

COPYRIGHT 2014 ALL RIGHT RESERVED REV: X01 PWB: DKNFC DATE: 1410-06

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. A

B

C

D

Title

Cover Sheet Size

Document Number

Date:

Thursday, March 06, 2014

Rev 0.3

LA-A901P Sheet E

1

of

53

A

B

C

D

E

Houston 14 UMA Dock Block Diagram Memory BUS (DDR3L)

eDP CONN 1

Reverse Type 1333/1600MHz

eDP

DDR3L-DIMM X2 BANK 0, 1, 2, 3

PAGE 23

1

PAGE 18 19

USB2.0[5]

INTEL Reduce Level ShifterPAGE 24

HDMI

HDMI CONN PAGE 24

DDI1 USB2.0[1]

BROADWELL ULT

PI3V713 VGA SW

VGA CONN VGA

E-Dock PAGE 34

USB2.0[3]

IDT VMM3320

DP 1.2

USB POWER SHARE

PAGE 22

2

USB SW NX3DV221GM

PAGE 31

PS8338B DP Sw

DP

USB2.0[1]_PS

PAGE 32

PAGE 26

PAGE 26

PAGE 23

TPS2544

USB

Camera

USB3.0[2] DOCK_USB2.0[3] USB2.0[3] USB3.0[4]

DDI2

USB2.0[0]

PAGE 25

USB3.0[1]

USB3.0/2.0 PS PAGE 32

PAGE 31

USB SW PI3USB3102ZLEX

PAGE 6~17

Intel Clarkville I218LM PAGE 28

HDA Codec ALC3235

WWAN/LTE Caching Card

PAGE 20

USH CONN

32M 4K sector

USB2.0[2]

SMSC SIO ECE5048

U XDP Port

PAGE 7

PAGE 9

Discrete TPM AT97SC3205

Automatic Power Switch (APS)PAGE 9

PAGE 27

PAGE 35

3

PAGE 27

W25Q32BVSSIQ

WIGIG_DP

PAGE 28

SATA3 Conn

PAGE 20

Trough eDP Cable

64M 4K sector

PAGE 30

Transformer

SATA Repeater W25Q64CVSSIQ

PCIE5_L0

USB2.0[7]

PAGE 21

PAGE 23

WLAN/BT/ WIGIG

PAGE 30

Combo Jack

PAGE 21

Dig. MIC

LPC

PCIE3

PCIE4

2

PAGE 21

SPI

O2 Micro OZ777FJ2LN-B PAGE 29

PCIE6_L1

PAGE 31

INT.Speaker

PCIE1

PCI Express BUS 3

HD Audio I/F

SATA1

Card reader

PCIE6_L0 SATA

USB3.0/2.0

PAGE 31

DAI LAN SATA1 DOCK_USB2.0[0] DOCK_USB2.0[3] DOCK_USB3.0[1]

PAGE 29

DOCK_USB3.0[1] DOCK_USB2.0[0]

USB3.0/2.0

WIGIG_DP

SD4.0

Trough eDP Cable

Free Fall sensor RJ45

PAGE 28

BC BUS

Smart Card

USH TPM1.2 BCM5882

TDA8034HN

4

BCM20793

RFID/NFC

PAGE 20

KB/TP CONN

SMSC KBC MEC5085

PAGE 37

DC/DC Interface

PAGE 38

PAGE 36

FAN CONN

Power On/Off SW & LED PAGE 39

PAGE 36

SPI


Fingerprint CONN

FP_USB

USH board PAGE 29

A

B

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. C

D

Title

Block diagram Size

Document Number

Date:


Rev 0.3

LA-A901P Sheet E

2

of

53

4

5

4

3

2

1

POWER STATES Signal State

D

C

S0 (Full ON) / M0

SLP S3#

SLP S4#

SLP S5#

SLP A#

HIGH

HIGH

HIGH

HIGH

ALWAYS PLANE

ON

M PLANE

SUS PLANE

RUN PLANE

ON

ON

ON

CLOCKS

PCIE

LOW

HIGH

HIGH

HIGH

ON

ON

ON

OFF

OFF

S4 (Suspend to DISK) / M3

LOW

LOW

HIGH

HIGH

ON

ON

OFF

OFF

OFF

S5 (SOFT OFF) / M3

LOW

LOW

LOW

HIGH

ON

ON

OFF

OFF

OFF

S3 (Suspend to RAM) / M-OFF

LOW

HIGH

HIGH

LOW

ON

OFF

ON

OFF

OFF

S4 (Suspend to DISK) / M-OFF

LOW

LOW

HIGH

LOW

ON

OFF

OFF

OFF

OFF

S5 (SOFT OFF) / M-OFF

LOW

LOW

LOW

LOW

ON

OFF

OFF

OFF

OFF

power plane

+5V_ALW

+3.3V_SUS

+5V_RUN

+3.3V_M

+3.3V_M

+1.35V_MEM

+3.3V_RUN

+1.05V_M

+1.05V_M

+3.3V_ALW_PCH

+0.675V_DDR_VTT

+3.3V_RTC_LDO

+1.05V_RUN

DESTINATION JUSB1-->Rear left

USB3.0 2

JUSB3-->Right

PCIE 1

USB3.0 3

MMI (CARD READER)

PCIE 2

USB3.0 4

JUSB2-->Rear Right

D

PM TABLE +3.3V_ALW

SATA

USB3.0 1

ON

S3 (Suspend to RAM) / M3

USB3.0

PCIE 3

LOM

PCIE 4

WLAN

PCIE 5

WIGIG L3

SATA 0

JDOCK1 (DOCK)

L2

SATA 1

JSATA1 (HDD)

L1

SATA 2

SSD Cache (PCIE)

L0

SATA 3

C

PCIE 6

(M-OFF)

SSD Cache (SATA/PCIE)/HCA

+VCC_CORE +1.5V_RUN

USB PORT#

State

B

S0

ON

ON

ON

ON

ON

S3

ON

ON

OFF

ON

OFF

S5 S4/AC

ON

OFF

OFF

ON

OFF

S5 S4/AC doesn't exist

OFF

OFF

OFF

OFF

OFF

BDW ULT

need to update Power Status and PM Table

USH

DESTINATION

0

JUSB1

1

JUSB3

2

WLAN + BT

3

JUSB2

4

Touch Screen

5

CAMERA

6

USH

7

WWAN

0

BIO

1

NA

B

A

A

DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

Title

Port assignment Size

4

3

2

Rev 0.3

LA-A901P Date:

5

Document Number Thursday, March 06, 2014

Sheet 1

3

of

53

5

4

3

2

RUN_ON

1

MPHYP_PWR_EN

SI3456 (QZ6)

TPS22965 (UZ7) D

D

EN_INVPWR

ADAPTER

FDC654P (QV1)

+BL_PWR_SRC +1.05V_RUN

A_ON

SY8208 (PU300)

+1.05V_MODPHY

+1.05V_M

+PWR_SRC

BATTERY

ALWON

TPS51285 (PU100)

+5V_ALW

C

C

CHARGER

TPS22966 (UZ2)

TPS22966 (UZ3)

APL3512 (UV24)

RUN_ON

RUN_ON

EN_LCDPWR

AUX_EN_WOWL

SUS_ON

SIO_SLP_LAN#

3.3V_WWAN_EN

TPS22966 (UZ8)

USB_PWR_SHR_EN#

TPS22966 (UZ9)

TPS2544 (UI3)

USB_PWR_EN1#

USB_PWR_EN2#

G547I2P81U (UI1)

G547I2P81U (UI2)

+0.675V_DDR_VTT

+3.3V_M

+3.3V_WWAN

+3.3V_ALW_PCH

+3.3V_SUS

+3.3V_LAN

+LCDVDD

+3.3V_WLAN

LP2301ALT1G (QZ1)

+3.3V_CAM

A

+3.3V_RUN

+5V_RUN

+5V_USB_CHG_PWR

+USB_LEFT_PWR

+USB_RIGHT_PWR

3.3V_TS_EN

+1.35V_MEM

3.3V_CAM_EN#

+VCC_CORE

0.675V_DDR_VTT_ON

B

SUS_ON

B

RT8207 (PU200)

H_VR_EN

ISL95813 (PU501)

PCH_ALW_ON

A_ON

+3.3V_ALW

LP2301ALT1G (QZ8)

+5V_TSP

A


www.vinafix.vn 5

4

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 3

2

Title

Power rails Size

Document Number

Date:


Rev 0.3

LA-A901P Sheet 1

4

of

53

5

4

3

2

1

2.2K

SMBUS Address [0x9a]

+3.3V_ALW_PCH

2.2K AP2

MEM_SMBCLK

AH1

MEM_SMBDATA

202

2N7002

DIMMA

200

2N7002 499

202

BDW

D

+3.3V_ALW_PCH

499 AN1 AH3

AU3

AK1

SML1_SMBCLK

3A

28

SML0DATA

31

LOM 53

SML1_SMBDATA

A5

SML0CLK

2.2K

XDP

51

2.2K

+3.3V_ALW_PCH

2.2K 2.2K

B6 3A

2.2K DOCK_SMB_CLK

A3

DOCK_SMB_DAT

+3.3V_RUN

2.2K 4

+3.3V_ALW

6 B4 1A 1A

D

DIMMB

200

G Sensor

C

C

B5 1B

A4

1B

2.2K

KBC

2.2K 1C 1C

A56 B59

PBAT_SMBCLK PBAT_SMBDAT

+3.3V_ALW 100 ohm

7

100 ohm

6

BATTERY CONN

2.2K

2.2K A50 1E

MEC 5085

B53 1E

B

+3.3V_SUS M9

USH_SMBCLK

L9

USH_SMBDAT

USH B

2B

A49

2B

B52

10K 10K B50 1G A47 1G

2D

+3.3V_ALW 9

CHARGER_SMBCLK

8

CHARGER_SMBDAT

Charger

B7

A

A

2D

A7

2.2K 2.2K 2A 2A

5

B48 B49

GPU_SMBDAT

DELL CONFIDENTIAL/PROPRIETARY

+3.3V_ALW

Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

GPU_SMBCLK

4

3

2

Title

SMbus Block diagram Size

Document Number

Date:


Rev 0.3

LA-A901P Sheet 1

5

of

53

5

4

3

SATA1

PCB

E-Dock

HDD

H12 UMA

NA

HDD

H12 Entry

E-Dock

HDD

H14 DSC

M2 3042 SATA-Cache(no HCA)

E-Dock

HDD

H14 UMA

M2 3042 2nd PCIe Lane for PCIe Cache

NA

HDD

H14D_En

NA

SW1

NA

HDD

H14U_En

NA

A B C G1 G2

E-Dock

HDD

H15 DSC

M2 3042 SATA-Cache(no HCA)

E-Dock

HDD

H15 UMA


NA

HDD

H15D_En

NA

NA

HDD

H15U_En

NA

Service Mode Switch: Add a switch to ME_FWP signal to unlock the ME region and allow the entire region of the SPI flash to be updated using FPT. +3.3V_ALW_PCH

1

ME_FWP_EC 2 1 ME_FWP @ RC301 0_0402_5% PT,ST pop RC2 and SW1; MP pop RC301

2

RC2 1K_0402_5%

<36>

+RTC_CELL

1 2 3 4 5

ME_FWP_EC

2

RC1 330K_0402_5%

1

ME_FWP

SS3-CMFTQR9_3P

ME_FWP PCH has internal 20K PD. (suspend power rail) FLASH DESCRIPTOR SECURITY OVERRIDE

PCH_INTVRMEN

LOW = ENABLE (DEFAULT) -->Pin1 & Pin3 short HIGH = DISABLE (ME can update) -->Pin2 & Pin3 short CC1 2

PCH_RTCX1_R

1 @ RC4

1

1

12P_0402_50V8J

High - Enable Internal VRs

2 1 1

2

RC9

CC2 2

2 2 20K_0402_5% 20K_0402_5% <9>

1

1

1U_0402_6.3V6K

CC4

<21>

CMOS place near DIMM CMOS_CLR1 B

Shunt

Clear CMOS

Open

Keep CMOS

PCH_JTAG_TDI 51_0402_5% PCH_JTAG_TDO 51_0402_5% PCH_JTAG_TMS 1 51_0402_5% PCH_JTAG_JTAGX 1 1K_0402_1% 1

RC15 2 RC16 2 @ RC18 2 @ RC21

1

+1.05V_M

@ RC300 1 2

SATA_RN0/PERN6_L3 SATA_RP0/PERP6_L3 SATA_TN0/PETN6_L3 SATA_TP0/PETP6_L3

RTC

SATA_RN1/PERN6_L2 SATA_RP1/PERP6_L2 SATA_TN1/PETN6_L2 SATA_TP1/PETP6_L2 PCH_AZ_BITCLK PCH_AZ_SYNC PCH_AZ_RST# PCH_AZ_CODEC_SDIN0 2

PCH_AZ_SDOUT 1K_0402_5%

PCH_JTAG_TRST# PCH_JTAG_TCK PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS PM_TEST_RST

<9>

10K_0402_5%

PCH_JTAG_TCK 51_0402_5%

to WWAN

NA SATA2/PCIE6_L1 to WWAN

M2 3030 WIGIG SATA3/PCIE6 L0 to WLAN M2 3042 (HCA & SATA-Cache)

D

to WWAN

M2 3030 WIGIG to WLAN NA SATA2/PCIE6_L1 to WWAN

M2 3030 WIGIG SATA3/PCIE6 L0 to WLAN M2 3042 (HCA & SATA-Cache)

to WWAN

M2 3030 WIGIG to WLAN Express card

AW8 AV11 AU8 AY10 AU12 AU11 AW10 AV10 AY8

PCH_JTAG_JTAGX

AU62 AE62 AD61 AE61 AD62 AL11 AC4 AE63 AV2

HDA_BCLK/I2S0_SCLK HDA_SYNC/I2S0_SFRM HDA_RST/I2S_MCLK AUDIO HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD HDA_SDO/I2S0_TXD HDA_DOCK_EN/I2S1_TXD HDA_DOCK_RST/I2S1_SFRM I2S1_SCLK

SATA

SATA_RN2/PERN6_L1 SATA_RP2/PERP6_L1 SATA_TN2/PETN6_L1 SATA_TP2/PETP6_L1 SATA_RN3/PERN6_L0 SATA_RP3/PERP6_L0 SATA_TN3/PETN6_L0 SATA_TP3/PETP6_L0 SATA0GP/GPIO34 SATA1GP/GPIO35 SATA2GP/GPIO36 SATA3GP/GPIO37

PCH_TRST PCH_TCK PCH_TDI PCH_TDO PCH_TMS RSVD RSVD JTAGX RSVD

JTAG

SATA_IREF RSVD RSVD SATA_RCOMP SATALED

J5 H5 B15 A15

to Express card

SATA_PRX_DKTX_N0_C SATA_PRX_DKTX_P0_C SATA_PTX_DKRX_N0_C SATA_PTX_DKRX_P0_C

J8 H8 A17 B17

SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 SATA_PTX_DRX_N1 SATA_PTX_DRX_P1

J6 H6 B14 C15 F5 E5 C17 D17 V1 U1 V6 AC1 A12 L11 K10 C12 U3

<34> <34> <34> <34>

for DOCK

<20> <20> <20> <20>

SATA HDD

PCIE_PRX_SATATX_N6_L1 PCIE_PRX_SATATX_P6_L1 PCIE_PTX_SATARX_N6_L1 PCIE_PTX_SATARX_P6_L1

<30> <30> <30> <30>

PCIE_PRX_SATATX_N6_L0 PCIE_PRX_SATATX_P6_L0 PCIE_PTX_SATARX_N6_L0 PCIE_PTX_SATARX_P6_L0

<30> <30> <30> <30>

SSD Cache (PCIE) SSD Cache/HCA (SATA/PCIE)

MPCIE_RST# <12> HDD_DET# <12,20> SATA2_PCIE6_L1 <12,35> mCARD_PCIE#_SATA <12,36>

B

+PCH_ASATA3PLL SATA_COMP SATA_ACT#

SATA_ACT#

+3.3V_RUN

<39>

RPC18 5 6 7 8

<10> DGPU_PWROK <10,20> HDD_FALL_INT <12> PCH_GPIO85 <12,23> 3.3V_TS_EN

2

1

2

PCH_AZ_CODEC_SDIN0 ME_FWP 1 RC11

<9> PCH_JTAG_TRST# <9> PCH_JTAG_TCK <9> PCH_JTAG_TDI <9> PCH_JTAG_TDO <9> PCH_JTAG_TMS

1

2

RTCX1 RTCX2 INTRUDER INTVRMEN SRTCRST RTCRST

PCH_RTCRST#

CMOS setting

+1.05V_M

RC14

AW5 AY5 AU6 AV7 AV6 AU7

2

@ CMOS1 SHORT PADS~D 1 2 1U_0402_6.3V6K

2

CC3

2

NA

M2 3042 (HCA & SATA-Cache)

BDW_ULT_DDR3L

@ UC1E

INTRUDER# PCH_INTVRMEN SRTCRST# PCH_RTCRST#

12P_0402_50V8J

1


C

PCH_RTCX2

1M_0402_5%

1 RC10 1 RC8

+RTC_CELL

2

YC1 32.768KHZ_12.5PF_9H03220008

Low - Enable External VRs

SATA2/PCIE6 L1 SATA3/PCIE6 L0

PCH_RTCX1

2 0_0402_5%

RC7 10M_0402_5%

C

1

INTVRMEN - INTEGRATED SUS 1.05V VRM ENABLE

1

SATA0

UMA SATA port

D

2

@ CC100 1U_0402_6.3V6K

4 3 2 1

10K_8P4R_5% BDW-ULT-DDR3L_BGA1168 5 OF 19

SATA Impedance Compensation +PCH_ASATA3PLL SATA_COMP 1 3.01K_0402_1%

HDA for Codec <21> <21>

2

RC19

PCH_AZ_CODEC_SYNC PCH_AZ_CODEC_RST# PCH_AZ_CODEC_BITCLK

A

CC5 @EMC@ 27P_0402_50V8J

1

<21> A

CAD note: Place the resistor within 500 mils of the PCH. Avoid routing next to clock pins.

PCH_AZ_SDOUT 33_0402_5% PCH_AZ_SYNC 1 2 RC20 33_0402_5% PCH_AZ_RST# 1 2 RC22 33_0402_5% PCH_AZ_BITCLK 1 EMC@ 2 RC23 33_0402_5% 1

PCH_AZ_CODEC_SDOUT

2

<21>


Reserve for EMI 5

2 RC17

4

3

2

Title

U (1/12) Size

Document Number

Date:


Rev 0.3

LA-A901P Sheet 1

6

of

53

5

4

3

2

1

+3.3V_RUN +3.3V_ALW_PCH BDW_ULT_DDR3L

<27>

PCH_SPI_CLK PCH_SPI_CS0# PCH_SPI_CS1# PCH_SPI_CS2# PCH_SPI_DO PCH_SPI_DIN PCH_SPI_DO2 PCH_SPI_DO3

PCH_SPI_CLK

D

<27> PCH_SPI_CS2# <27> PCH_SPI_DO <27> PCH_SPI_DIN

AU14 AW12 AY12 AW11 AV12

AA3 Y7 Y4 AC2 AA2 AA4 Y6 AF1

LAD0 LAD1 LAD2 LAD3 LFRAME

LPC SMBUS

SPI_CLK SPI_CS0 SPI_CS1 SPI_CS2 SPI_MOSI SPI_MISO SPI_IO2 SPI_IO3

SPI

AN2 AP2 AH1 AL2 AN1 AK1 AU4 AU3 AH3

SMBALERT/GPIO11 SMBCLK SMBDATA SML0ALERT/GPIO60 SML0CLK SML0DATA SML1ALERT/PCHHOT/GPIO73 SML1CLK/GPIO75 SML1DATA/GPIO74

C-LINK

<11> MEM_SMBCLK

SML0_SMBCLK SML0_SMBDATA

SML0_SMBCLK <28> SML0_SMBDATA <28> PCH_GPIO73 <9> SML1_SMBCLK <36> SML1_SMBDATA <36>

SML1_SMBCLK SML1_SMBDATA PCH_CL_CLK1 PCH_CL_DATA1 PCH_CL_RST1#

AF2 AD2 AF4

CL_CLK CL_DATA CL_RST

PCH_SMB_ALERT#

MEM_SMBCLK MEM_SMBDATA

2

LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 LPC_LFRAME#

<35,36> LPC_LAD0 <35,36> LPC_LAD1 <35,36> LPC_LAD2 <35,36> LPC_LAD3 <35,36> LPC_LFRAME#

6 5

@ UC1G

RPC14

1

DDR_XDP_WAN_SMBCLK

MEM_SMBCLK MEM_SMBDATA SML1_SMBCLK SML1_SMBDATA

<9,18,19,20>

QC1A DMN66D0LDW-7_SOT363-6

1 2 3 4

8 7 6 5

2.2K_0804_8P4R_5% MEM_SMBDATA 3

4

DDR_XDP_WAN_SMBDAT

<9,18,19,20>

SML0_SMBCLK 499_0402_1% SML0_SMBDATA 499_0402_1%

QC1B DMN66D0LDW-7_SOT363-6

PCH_CL_CLK1 <30> PCH_CL_DATA1 <30> PCH_CL_RST1# <30>

2

1

2

1

RC33 D

RC34

+3.3V_SPI +3.3V_SPI

2 SPI_PCH_DO2 1K_0402_5% 2 SPI_PCH_DO3 1K_0402_5%

1 RC29

1 RC31

1

BDW-ULT-DDR3L_BGA1168 7 OF 19

64Mb Flash ROM RPC11

SPI_CLK32

SPI_PCH_DIN SPI_PCH_DO SPI_PCH_CLK SPI_PCH_DO3

SPI_CLK64

1 2 3 4

CC6 2

0.1U_0402_25V6

UC2 SPI_DIN64 SPI_DO64 SPI_CLK64 SPI_PCH_DO3_64

8 7 6 5

SPI_PCH_CS0# @ RC35 1

2 0_0402_5%

SPI_PCH_DO2

2 33_0402_5%

RC38 1

SPI_PCH_CS0#_R SPI_DIN64 SPI_PCH_DO2_64

1 2 3 4

/CS DO(IO1) /WP(IO2) GND

8 7 6 5

VCC /HOLD(IO3) CLK DI(IO0)

SPI_PCH_DO3_64 SPI_CLK64 SPI_DO64

2 1 2 1

1 2 1

@EMC@ @EMC@ CC10 RC62 33P_0402_50V8J 33_0402_5%

C

@EMC@ @EMC@ CC9 RC61 33P_0402_50V8J 33_0402_5%

2

W25Q64FVSSIQ_SO8 33_0804_8P4R_5% +3.3V_SPI

SOFTWARE TAA

VPRO@ CC7 2

VPRO@ RPC12 SPI_PCH_DO3 SPI_PCH_CLK SPI_PCH_DO SPI_PCH_DIN

1 2 3 4

1

32Mb Flash ROM

SPI_PCH_DO3_32 SPI_CLK32 SPI_DO32 SPI_DIN32

8 7 6 5

SPI_PCH_CS1# SPI_PCH_DO2

VPRO@ RC50 1 VPRO@ RC55 1

UC3 SPI_PCH_CS1#_R SPI_DIN32 SPI_PCH_DO2_32

2 0_0402_5% 2 33_0402_5%

33_0804_8P4R_5%

1 2 3 4

0.1U_0402_25V6

VPRO@

/CS VCC DO/IO1 /HOLD/IO3 /WP/IO2 CLK GND DI/IO0 W25Q32FVSSIQ_SO8

8 7 6 5

SPI_PCH_DO3_32 SPI_CLK32 SPI_DO32 C

1

MMI --->

+3.3V_RUN +3.3V_RUN

10/100/1G LAN ---> WLAN (NGFF1)--->

RPC6

4 3 2 1

5 6 7 8

PCH_GPIO69 <12> USH_DET# <12,27> USB# <12> LCD_CBL_DET# <12,23>

WGIG (NGFF1)--->

10K_8P4R_5%

HCA/PCIe cache (NGFF2)--->

B

PCB

PCIE1

H12 UMA SD card

PCIE2 PCIE3 PCIE4 NA

LOM

WLAN

PCIE5 WIGIG

C43 C42 U2

<29> CLK_PCIE_MMI# <29> CLK_PCIE_MMI <12,29> MMICLK_REQ#

RC66 1

2 10K_0402_5%

B41 A41 PCH_GPIO19 Y5 C41 B42 AD1

<28> CLK_PCIE_LAN# <28> CLK_PCIE_LAN <12,28> LANCLK_REQ#

B38 C37 N1

<30> CLK_PCIE_WLAN# <30> CLK_PCIE_WLAN <12,30> WLANCLK_REQ#

A39 B39 U5

<30> CLK_PCIE_WIGIG# <30> CLK_PCIE_WIGIG <12,30> WIGIGCLK_REQ# <30> CLK_PCIE_SATA# <30> CLK_PCIE_SATA <30> SATACLK_REQ# +3.3V_RUN

PCIE6 M2 3042 (HCA & SATA-Cache)

H12 Entry SD card

NA

LOM

WLAN

WIGIG

NA

H14 DSC SD card

NA

LOM

WLAN

GPU

WIGIG

B37 A37 T2 RC68

1

2 10K_0402_5%

CLKOUT_PCIE_N0 CLKOUT_PCIE_P0 PCIECLKRQ0/GPIO18

XTAL24_IN XTAL24_OUT RSVD RSVD DIFFCLK_BIASREF

CLKOUT_PCIE_N1 CLKOUT_PCIE_P1 PCIECLKRQ1/GPIO19 CLKOUT_PCIE_N2 CLKOUT_PCIE_P2 PCIECLKRQ2/GPIO20

CLOCK SIGNALS


TESTLOW_C35 TESTLOW_C34 TESTLOW_AK8 TESTLOW_AL8 CLKOUT_LPC_0 CLKOUT_LPC_1 CLKOUT_ITPXDP CLKOUT_ITPXDP_P


A25 B25

XTAL24_IN XTAL24_OUT

A

H14 UMA SD card

NA

LOM

WLAN

WIGIG

H14D_En SD card

NA

LOM

WLAN

GPU

WIGIG

H14U_En SD card

NA

LOM

WLAN

WIGIG

NA

H15 DSC SD card

NA

LOM

WLAN

GPU

WIGIG

H15 UMA SD card

NA

LOM

WLAN

WIGIG


H15D_En SD card

NA

LOM

WLAN

GPU

WIGIG

H15U_En SD card 5

NA

LOM

WLAN

WIGIG

NA 4

YC2 24MHZ_12PF_X3G024000DC1H

1 @ RC65

K21 M21 C26

CLK_BIASREF

C35 C34 AK8 AL8

M_TESTLOW1 M_TESTLOW2 M_TESTLOW3 M_TESTLOW4

AN15 AP15

PCI_CLK_LPC_0 PCI_CLK_LPC_1

CC11 2 1

2 XTAL24_OUT_R 0_0402_5%

15P_0402_50V8J

+PCH_VCCACLKPLL CLK_BIASREF 1 3.01K_0402_1% M_TESTLOW1 M_TESTLOW2 M_TESTLOW3 M_TESTLOW4

B35 A35

RC240 RC241 RC242 RC243

2 RC69

1 1 1 1

2 2 2 2

10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%


B


PCI_CLK_LPC_0 EMC@

RC72 1

2 22_0402_5%

EMC@

RC74 1

2 22_0402_5%

EMC@

RC67 1

2 22_0402_5%

EMC@

RC70 1

2 22_0402_5%

CLK_PCI_SIO CLK_PCI_MEC

<35> <36>

JSPI1

2 PCI_CLK_LPC_1

CLK_PCI_LPDEBUG CLK_PCI_DOCK

1 0_0402_5% 1 0_0402_5% 1 0_0402_5% 1 0_0402_5% 1 0_0402_5% 1 0_0402_5% 1 0_0402_5%

RC224

<36>

2 RC225

<34>

2 RC226

2


3 4

BDW_ULT_DDR3L

@ UC1F

1

1 2

PCIECLK for UMA

RC63 1M_0402_5%

2

CC8 2

15P_0402_50V8J

RC227

2 CLK_PCI_SIO 2 12P_0402_50V8J

1 @EMC@ CC12

RC228

RC230

2 RC229

2 CLK_PCI_MEC 12P_0402_50V8J

2

1 @EMC@ CC13

CLK_PCI_LPDEBUG 12P_0402_50V8J

2

1 @EMC@ CC14

CLK_PCI_DOCK 12P_0402_50V8J

2

SPI_PCH_CS1# PCH_SPI_CS1# SPI_PCH_DO PCH_SPI_DO SPI_PCH_DIN PCH_SPI_DIN SPI_PCH_CLK PCH_SPI_CLK SPI_PCH_CS0# PCH_SPI_CS0# SPI_PCH_DO2 PCH_SPI_DO2 SPI_PCH_DO3 PCH_SPI_DO3

+3.3V_SPI +3.3V_M

2

1 0_0402_5%

RC231

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

1 @EMC@ CC15

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

SPI TPM LPC_0

LPC_1

SIO

DOCK

MEC

DEBUG

GND1 GND2 A

TYCO_2-2041070-0 CONN@

Reserve for EMI

DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 3

2

Title

U (2/12) Size

Document Number

Date:


LA-A901P Sheet 1

Rev 0.3 7

of

53

5

4

D

@ UC1C <18>

DDR_A_D[0..63]

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

C

B

AH63 AH62 AK63 AK62 AH61 AH60 AK61 AK60 AM63 AM62 AP63 AP62 AM61 AM60 AP61 AP60 AP58 AR58 AM57 AK57 AL58 AK58 AR57 AN57 AP55 AR55 AM54 AK54 AL55 AK55 AR54 AN54 AY58 AW58 AY56 AW56 AV58 AU58 AV56 AU56 AY54 AW54 AY52 AW52 AV54 AU54 AV52 AU52 AK40 AK42 AM43 AM45 AK45 AK43 AM40 AM42 AM46 AK46 AM49 AK49 AM48 AK48 AM51 AK51

SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

3

BDW_ULT_DDR3L

<19>

SA_CLK#0 SA_CLK0 SA_CLK#1 SA_CLK1 SA_CKE0 SA_CKE1 SA_CKE2 SA_CKE3 SA_CS#0 SA_CS#1 SA_ODT0 SA_RAS SA_WE SA_CAS SA_BA0 SA_BA1 SA_BA2 SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8 SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15

DDR CHANNEL A

SA_DQSN0 SA_DQSN1 SA_DQSN2 SA_DQSN3 SA_DQSN4 SA_DQSN5 SA_DQSN6 SA_DQSN7 SA_DQSP0 SA_DQSP1 SA_DQSP2 SA_DQSP3 SA_DQSP4 SA_DQSP5 SA_DQSP6 SA_DQSP7 SM_VREF_CA SM_VREF_DQ0 SM_VREF_DQ1

AU37 AV37 AW36 AY36

M_CLK_DDR#0 M_CLK_DDR0 M_CLK_DDR#1 M_CLK_DDR1

AU43 AW43 AY42 AY43

DDR_CKE0_DIMMA DDR_CKE1_DIMMA

AP33 AR32

DDR_CS0_DIMMA# DDR_CS1_DIMMA#

2

M_CLK_DDR#0 <18> M_CLK_DDR0 <18> M_CLK_DDR#1 <18> M_CLK_DDR1 <18> DDR_CKE0_DIMMA DDR_CKE1_DIMMA

<18> <18>

DDR_CS0_DIMMA# DDR_CS1_DIMMA#

<18> <18>

AP32 AY34 AW34 AU34

DDR_A_RAS# DDR_A_WE# DDR_A_CAS#

AU35 AV35 AY41

DDR_A_BS0 DDR_A_BS1 DDR_A_BS2

AU36 AY37 AR38 AP36 AU39 AR36 AV40 AW39 AY39 AU40 AP35 AW41 AU41 AR35 AV42 AU42

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

AJ61 AN62 AM58 AM55 AV57 AV53 AL43 AL48

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

AJ62 AN61 AN58 AN55 AW57 AW53 AL42 AL49

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

AP49 AR51 AP51

DDR_A_RAS# DDR_A_WE# DDR_A_CAS#

<18> <18> <18>

DDR_A_BS0 <18> DDR_A_BS1 <18> DDR_A_BS2 <18> DDR_A_MA[0..15]

DDR_A_DQS#[0..7]

DDR_A_DQS[0..7]

@ UC1D

DDR_B_D[0..63]

<18>

<18>

<18>

+SM_VREF_CA +SM_VREF_DQ0 +SM_VREF_DQ1


DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

AY31 AW31 AY29 AW29 AV31 AU31 AV29 AU29 AY27 AW27 AY25 AW25 AV27 AU27 AV25 AU25 AM29 AK29 AL28 AK28 AR29 AN29 AR28 AP28 AN26 AR26 AR25 AP25 AK26 AM26 AK25 AL25 AY23 AW23 AY21 AW21 AV23 AU23 AV21 AU21 AY19 AW19 AY17 AW17 AV19 AU19 AV17 AU17 AR21 AR22 AL21 AM22 AN22 AP21 AK21 AK22 AN20 AR20 AK18 AL18 AK20 AM20 AR18 AP18

1

D

BDW_ULT_DDR3L

SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

SB_CK#0 SB_CK0 SB_CK#1 SB_CK1 SB_CKE0 SB_CKE1 SB_CKE2 SB_CKE3 SB_CS#0 SB_CS#1 SB_ODT0 SB_RAS SB_WE SB_CAS SB_BA0 SB_BA1 SB_BA2

DDR CHANNEL B

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15 SB_DQSN0 SB_DQSN1 SB_DQSN2 SB_DQSN3 SB_DQSN4 SB_DQSN5 SB_DQSN6 SB_DQSN7 SB_DQSP0 SB_DQSP1 SB_DQSP2 SB_DQSP3 SB_DQSP4 SB_DQSP5 SB_DQSP6 SB_DQSP7

AM38 AN38 AK38 AL38

M_CLK_DDR#2 M_CLK_DDR2 M_CLK_DDR#3 M_CLK_DDR3

AY49 AU50 AW49 AV50

DDR_CKE2_DIMMB DDR_CKE3_DIMMB

AM32 AK32

DDR_CS2_DIMMB# DDR_CS3_DIMMB#

M_CLK_DDR#2 <19> M_CLK_DDR2 <19> M_CLK_DDR#3 <19> M_CLK_DDR3 <19> DDR_CKE2_DIMMB DDR_CKE3_DIMMB

<19> <19>

DDR_CS2_DIMMB# DDR_CS3_DIMMB#

<19> <19>

AL32 AM35 AK35 AM33

DDR_B_RAS# DDR_B_WE# DDR_B_CAS#

AL35 AM36 AU49

DDR_B_BS0 DDR_B_BS1 DDR_B_BS2

AP40 AR40 AP42 AR42 AR45 AP45 AW46 AY46 AY47 AU46 AK36 AV47 AU47 AK33 AR46 AP46

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

AW30 AV26 AN28 AN25 AW22 AV18 AN21 AN18

DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_DQS#[0..7]

<19>

AV30 AW26 AM28 AM25 AV22 AW18 AM21 AM18

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

DDR_B_DQS[0..7]

<19>

DDR_B_RAS# DDR_B_WE# DDR_B_CAS#

<19> <19> <19>

DDR_B_BS0 <19> DDR_B_BS1 <19> DDR_B_BS2 <19> DDR_B_MA[0..15]

<19>

C

B


A

A


4

3

2

Title

U (3/12) Size

Document Number

Date:


Rev 0.3

LA-A901P Sheet 1

8

of

53

5

4

3

1

@ RC77

2

1

2 0_0402_5% +3.3V_RUN

Fix Intel 7260 can not detect issue. It will cause “floating” situation before 3V_RUN coming of AND gate

5

PCH_PLTRST#_EC

+3.3V_ALW2

<27,30,35,36>

2

@ RC304 100K_0402_5%

SIO_SLP_A#

2

+PCH_VCCDSW3_3

<36>

PM_APWROK

PM_APWROK

1

2

@ RC26

+3.3V_ALW_PCH

PM_APWROK_L 0_0402_5%

1 2

B A

RPC1

4 3 2 1

5 6 7 8

PCH_GPIO73 <7> SIO_EXT_WAKE# <12,36> PCH_GPIO46 <12>

PCH_PCIE_WAKE#

<43> <22>

10K_8P4R_5%

@ RC219 1 @ RC87 1 @ RC88 1 @ RC89 1

PLTRST_VMM2320# <27> PLTRST_USH# <29> PLTRST_MMI# <28> PLTRST_LAN#

2 0_0402_5% 2 0_0402_5% 2 0_0402_5% 2 0_0402_5%

1

1.05V_M_PWRGD

4

O 3

D

4PCH_PLTRST#_EC

PM_APWROK_R

1

A UC5 TC7SH08FU_SSOP5~D

@ UC4 74AHC1G09GW_TSSOP5

+RTC_CELL

O

5

B

2

P

1

1

A

SYS_RESET#

4

P

PCH_PLTRST#

O

G

1

B

3

RC81 @ RC82

@ RC80

2

UC6 TC7SH08FU_SSOP5~D

1

D

DSWODVREN

2 0_0402_5%

@ RC27

DSWODVREN - ON DIE DSW VR ENABLE

PCH_PLTRST#

HIGH = ENABLED (DEFAULT) LOW = DISABLED

2 PCH_RSMRST#_Q 47K_0402_5%

RC91

RC78 330K_0402_5%

1

1 ME_RESET# 8.2K_0402_5%

2

3

1

2

G

XDP_DBRESET# ME_SUS_PWR_ACK 10K_0402_5% 2 SUSACK# 10K_0402_5% 2 SUS_STAT#/LPD# 10K_0402_5%

1 RC79

P

+3.3V_ALW_PCH

G

5

+3.3V_RUN

BDW_ULT_DDR3L

@ UC1H

SYSTEM POWER MANAGEMENT

<36> +3.3V_RUN

<36> <15,36>

SYS_PWROK RESET_OUT#

PM_APWROK_R PCH_PLTRST#

ME_RESET# 8.2K_0402_5%

<37> PCH_RSMRST#_Q <36> ME_SUS_PWR_ACK <36> SIO_PWRBTN# <12,36> AC_PRESENT <11> PCH_BATLOW# <35>

SIO_SLP_WLAN#

PCH_RSMRST#_Q ME_SUS_PWR_ACK SIO_PWRBTN# AC_PRESENT SIO_SLP_S0# SIO_SLP_WLAN#

AW6 AV4 AL7 AJ8 AN4 AF3 AM5

+3.3V_RUN

2

CLKRUN/GPIO32 SUS_STAT/GPIO61 SUSCLK/GPIO62 SLP_S5/GPIO63

RSMRST SUSWARN/SUSPWRDNACK/GPIO30 PWRBTN ARESENT/GPIO31 BATLOW/GPIO72 SLP_S0 SLP_WLAN/GPIO29

UC7 CXDP@

14

PCH_JTAG_TDI 1 RC99 CXDP@

2 TDI_XDP_R 0_0402_5%

5 4

RUNPWROK <6>

PCH_JTAG_TMS

PCH_JTAG_TMS

9 10

RUNPWROK TRST#_XDP

<35,36>

RUNPWROK

3

1B

U_XDP_TDO

12 13

RUNPWROK

1OE 2A

6

2B

U_XDP_TDI

3A

8

3B

Place near JXDP1

<13> <13>

CFG0 CFG1

<13> <13>

CFG2 CFG3

11

4B

4OE

U_XDP_TRST#

RC5 need to close to JU1

7

GND

<15>

15

H_VCCST_PWRGD

CFG2 CFG3 XDP_OBS0_R XDP_OBS1_R

3OE 4A

CFG0 CFG1

<13> <13>

CFG4 CFG5

CFG4 CFG5

CFG6 <13> CFG6 2 1K_0402_5% RC102 1 CFG7 <13> CFG7 CXDP@ H_UPWRGD @ RC103 1 H_VCCST_PWRGD_XDP 2 1K_0402_5% SIO_PWRBTN#

74CBTLV3126BQ_DHVQFN14_2P5X3 <15>

PCH_JTAG_TRST#

<6>

PCH_JTAG_JTAGX

H_CATERR# 49.9_0402_1% H_PROCHOT# 2 62_0402_5%

2

U_XDP_TRST# 1 RC109 CXDP@

2

U_XDP_TCLK 1 RC112 CXDP@

0_0402_5%

0_0402_5%

SYS_PWROK

U_XDP_TCLK

RC116

TDO_XDP 1 RC115 @

2 0_0402_5% PCH_JTAG_TDO 2 0_0402_5%

U_XDP_TCLK 1 RC119 @

BDW_ULT_DDR3L

@ UC1B EMI request add <36>

1

H_PROCHOT#

H_CATERR# PECI_EC

PECI_EC

1

2

RC121

@EMC@ CC83 100P_0402_50V8J

RC123 10K_0402_5%

2

<36,45,46>

H_PROCHOT#_R 56_0402_5% H_UPWRGD

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

CAD Note: Avoid stub in the PWRGD path while placing resistors RC123

PCH_RTCRST#

PCH_RTCRST#

SYS_RESET# SIO_SLP_S0#

C

<18,19> DDR3_DRAMRST# <18> DDR_PG_CTRL

A

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60

CFG17 CFG16

CFG17 CFG16

CFG8 CFG9

CFG8 CFG9

CFG10 CFG11

CFG10 CFG11

<13> <13>

CFG19 CFG18

CFG19 CFG18

<13> <13>

CFG12 CFG13

CFG12 CFG13

<13> <13>

CFG14 CFG15

CFG14 CFG15

<13> <13>

XDP_RST#_R XDP_DBRESET#

D61 K61 N62

K63

C61

AU60 AV60 AU61 AV15 AV61

PROC_DETECT CATERR PECI

PROCHOT

PROWRGD

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 SM_DRAMRST SM_PG_CNTL1

MISC

PRDY PREQ PROC_TCK PROC_TMS PROC_TRST PROC_TDI PROC_TDO

JTAG THERMAL

J62 K62 E60 E61 E59 F63 F62

U_XDP_PRDY# U_XDP_PREQ# U_XDP_TCLK U_XDP_TMS U_XDP_TRST# U_XDP_TDI U_XDP_TDO

J60 H60 H61 H62 K59 H63 K60 J61

XDP_OBS0_R XDP_OBS1_R XDP_OBS2_R XDP_OBS3_R XDP_OBS4_R XDP_OBS5_R XDP_OBS6_R XDP_OBS7_R

PWR

BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7

DDR3L

<13> <13> <13> <13>

2 RC106 CXDP@

TDO_XDP TRST#_XDP PCH_JTAG_TDI PCH_JTAG_TMS CFG3_R 1 RC113 CXDP@

1

PCH_PLTRST#_EC 1K_0402_5%

2 CFG3 1K_0402_5%

+1.05V_RUN

1

B

@ RC117

Place near JXDP1.48 XDP_DBRESET#

1 2

@ CC22 0.1U_0402_25V6

2

2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 GND GND CONN@ ACES_50506-01841-P01

POWER_SW#_MB

TDO_XDP 2 51_0402_5%

SYS_PWROK

H_UPWRGD

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

CC21 CXDP@ 0.1U_0402_25V6

1

H_PROCHOT#

@EMC@ CC20 22P_0402_50V8J

1

GND0 GND1 OBSFN_A0 OBSFN_C0 OBSFN_A1 OBSFN_C1 GND2 GND3 OBSDATA_A0 OBSDATA_C0 OBSDATA_A1 OBSDATA_C1 GND4 GND5 OBSDATA_A2 OBSDATA_C2 OBSDATA_A3 OBSDATA_C3 GND6 GND7 OBSFN_B0 OBSFN_D0 OBSFN_B1 OBSFN_D1 GND8 GND9 OBSDATA_B0 OBSDATA_D0 OBSDATA_B1 OBSDATA_D1 GND10 GND11 OBSDATA_B2 OBSDATA_D2 OBSDATA_B3 OBSDATA_D3 GND12 GND13 PWRGOOD/HOOK0 ITPCLK/HOOK4 HOOK1 ITPCLK#/HOOK5 VCC_OBS_AB VCC_OBS_CD HOOK2 RESET#/HOOK6 HOOK3 DBR#/HOOK7 GND14 GND15 SDA TD0 SCL TRST# TCK1 TDI TCK0 TMS GND16 GND17 SAMTE_BSH-030-01-L-D-A CONN@

CXDP@ RC120 1K_0402_5%

PCH_JTAG_TCK 2 0_0402_5%

1

<6> <36,39>

+3.3V_ALW_PCH

TDI_XDP_R 1 RC118 @

2

1 B

<6>

U_PWR_DEBUG#

<7,18,19,20> DDR_XDP_WAN_SMBDAT <7,18,19,20> DDR_XDP_WAN_SMBCLK <6> PCH_JTAG_TCK

2

@ RC114

SIO_SLP_S5# SIO_SLP_S4# SIO_SLP_A#

+1.05V_RUN

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59

U_XDP_PREQ# U_XDP_PRDY#

U_XDP_TMS

reference Shark Bay ULT Validation Customer Debug Port Implementation Requirement Rev 1.0

1

SIO_SLP_S3#

JXDP1

2OE

GND PAD

+1.05V_VCCST

+3.3V_ALW_PCH +PCH_VCCDSW3_3

+PCH_VCCDSW3_3

<30>

2

PCH_JTAG_TDI

AJ6 AT4 AL5 AP4 AJ7

+1.05V_RUN

1A

2

1

RUNPWROK <6>

CLKRUN# <12,35,36> SUS_STAT#/LPD# SUSCLK_R 1 2 SUSCLK SIO_SLP_S5# @ RC136 0_0402_5% SIO_SLP_S5# <36> T8 PAD~D @ T9 PAD~D @ SIO_SLP_S4# SIO_SLP_S4# <36> SIO_SLP_S3# SIO_SLP_S3# <36> SIO_SLP_A# SIO_SLP_A# <36> SIO_SLP_SUS# SIO_SLP_SUS# <36> SIO_SLP_LAN# SIO_SLP_LAN# <28,36>

VCC 1

2

@ CC19 0.1U_0402_25V6

2 TDO_XDP 0_0402_5%

1 RC98 CXDP@

V5 AG4 AE6 AP5

JAPS1 PCH_DPWROK <36> PCH_PCIE_WAKE# <35,36>

+1.05V_RUN

@ CC18 0.1U_0402_25V6

PCH_JTAG_TDO

DSWODVREN PCH_DPWROK PCH_PCIE_WAKE#


CC17 CXDP@ 1

0.1U_0402_25V6

<6>

SLP_S4 SLP_S3 SLP_A SLP_SUS SLP_LAN

AW7 AV5 AJ5

1

C

DSWVRMEN DPWROK WAKE

1

2

SUSACK SYS_RESET SYS_PWROK PCH_PWROK APWROK PLTRST

2

1 @ RC95

AK2 AC3 AG2 AY7 AB5 AG7

SUSACK# SYS_RESET# SYS_PWROK

SUSACK#

Place near JXDP1.47

+3.3V_RUN XDP_DBRESET# 2 1K_0402_5%

1 RC122 +1.05V_RUN

PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D

T10 T11 T12 T13 T14 T15

U_XDP_TMS 51_0402_5% U_XDP_TDI 51_0402_5% U_XDP_PREQ# 51_0402_5% U_XDP_TDO 51_0402_5%

@ @ @ @ @ @


2

1 @ RC124

2

1 @ RC125

2

1 @ RC126

2

1

RC127

U_XDP_TCLK 2 51_0402_5% U_XDP_TRST# 2 51_0402_5%

1

RC128

1 @ RC129 A

DDR3 COMPENSATION SIGNALS 200_0402_1% 121_0402_1% 100_0402_1%

2

1 RC130

SM_RCOMP0

2

1 RC131

SM_RCOMP1

2

1 RC132

SM_RCOMP2


CAD Note: Trace width=12~15 mil, Spcing=20 mils Max trace length= 500 mil

5


3

2

Title

U (4/12) Size

Document Number

Date:


Rev 0.3

LA-A901P Sheet 1

9

of

53

5

4

3

2

1

D

D

BDW_ULT_DDR3L

@ UC1A

C54 C55 B58 C58 B55 A55 A57 B57

<24> DDI1_LANE_N0 <24> DDI1_LANE_P0 <24> DDI1_LANE_N1 <24> DDI1_LANE_P1 <24> DDI1_LANE_N2 <24> DDI1_LANE_P2 <24> DDI1_LANE_N3 <24> DDI1_LANE_P3

C51 C50 C53 B54 C49 B50 A53 B53

<25> DDI2_LANE_N0 <25> DDI2_LANE_P0 <25> DDI2_LANE_N1 <25> DDI2_LANE_P1 <25> DDI2_LANE_N2 <25> DDI2_LANE_P2 <25> DDI2_LANE_N3 <25> DDI2_LANE_P3

DDI1_TXN0 DDI1_TXP0 DDI1_TXN1 DDI1_TXP1 DDI1_TXN2 DDI1_TXP2 DDI1_TXN3 DDI1_TXP3

EDP_TXN0 EDP_TXP0 EDP_TXN1 EDP_TXP1

DDI

EDP

DDI2_TXN0 DDI2_TXP0 DDI2_TXN1 DDI2_TXP1 DDI2_TXN2 DDI2_TXP2 DDI2_TXN3 DDI2_TXP3

EDP_TXN2 EDP_TXP2 EDP_TXN3 EDP_TXP3 EDP_AUXN EDP_AUXP EDP_RCOMP EDP_DISP_UTIL

C45 B46 A47 B47

EDP_U_LANE_N0 EDP_U_LANE_P0 EDP_U_LANE_N1 EDP_U_LANE_P1

EDP_U_LANE_N0 EDP_U_LANE_P0 EDP_U_LANE_N1 EDP_U_LANE_P1

<23> <23> <23> <23>

COMPENSATION PU FOR eDP +VCCIOA_OUT

C47 C46 A49 B49

EDP_COMP 2 24.9_0402_1%

A45 B45

EDP_U_AUX# EDP_U_AUX

D20 A43

EDP_COMP

1 RC133

CAD Note:Trace width=20 mils ,Spacing=25mil, Max length=100 mils.

EDP_U_AUX# <23> EDP_U_AUX <23>

C

C


+3.3V_RUN RPC15 5 6 7 8

4 3 2 1

CAM_MIC_CBL_DET# <12,23> GPU_GC6_FB_EN <12> 3.3V_TP_EN

10K_8P4R_5% <23> EDP_BIA_PWM <23> _BKLEN <23,36> ENVDD_PCH

<12,27> 1

2

@ RC139 2

1

@ RC140

ENVDD_PCH 100K_0402_5% PCH_GPIO53 1K_0402_5%

BDW_ULT_DDR3L

@ UC1I

+3.3V_RUN

<12>

<6,20>

<12>

EDP_BIA_PWM _BKLEN ENVDD_PCH

U6 P4 N4 N2 AD4

LESS_DET# <6> DGPU_PWROK HDD_FALL_INT <12> PCH_GPIO80 @ T16 PAD~D TOUCHPAD_INTR# <12> PCH_GPIO52 PCH_GPIO53

B

B8 A9 C6

U7 L1 L3 R5 L4

EDP_BKLCTL EDP_BKLEN EDP_VDDEN

DDPB_CTRLCLK DDPB_CTRLDATA DDPC_CTRLCLK DDPC_CTRLDATA

eDP SIDEBAND

PIRQA/GPIO77 PIRQB/GPIO78 PIRQC/GPIO79 PIRQD/GPIO80 PME

DISPLAY PCIE

DDPB_AUXN DDPC_AUXN DDPB_AUXP DDPC_AUXP

B9 C9 D9 D11

U_DPB_CTRLCLK U_DPB_CTRLDAT U_DPC_CTRLCLK U_DPC_CTRLDAT

U_DPB_CTRLCLK <24> U_DPB_CTRLDAT <24>

C5 B6 B5 A6

U_DPB_AUX# U_DPC_AUX# U_DPB_AUX U_DPC_AUX

U_DPC_AUX#

C8 A8 D6

DPB_HPD DPC_HPD EDP_U_HPD

U_DPB_CTRLDAT U_DPB_CTRLCLK U_DPC_CTRLCLK U_DPC_CTRLDAT

RPC2 1 2 3 4

8 7 6 5

2.2K_0804_8P4R_5%

U_DPC_AUX

<25> <25>

RPC20

U_DPB_AUX# U_DPB_AUX U_DPC_AUX U_DPC_AUX#

1 2 3 4

8 7 6 5

100K_0804_8P4R_5%

GPIO55 GPIO52 GPIO54 GPIO51 GPIO53

DDPB_HPD DDPC_HPD EDP_HPD

DPB_HPD <24> DPC_HPD <25> EDP_U_HPD <23>

EDP_U_HPD

100K_0402_5% 2

1 RC141

DPC_HPD

100K_0402_5% 2

1 RC142

B


A

A


4

3

2

Title

U (5/12) Size

Document Number

Date:


Rev 0.3

LA-A901P Sheet 1

10

of

53

5

4

3

2

1

PCIE for UMA D

WIGIG --->

<30> <30> <30> <30>

PCIE_PRX_WIGIGTX_N5 PCIE_PRX_WIGIGTX_P5 PCIE_PTX_WIGIGRX_N5 PCIE_PTX_WIGIGRX_P5

PCIE_PRX_WIGIGTX_N5 PCIE_PRX_WIGIGTX_P5

F10 E10

PCIE_PTX_WIGIGRX_N5 PCIE_PTX_WIGIGRX_P5

C23 C22 F8 E8 B23 A23 H10 G10 B21 C21 E6 F6 B22 A21

10/100/1G LAN ---> C

WLAN (Mini Card 2)--->

MMI -->

<28> <28>

PCIE_PRX_GLANTX_N3 PCIE_PRX_GLANTX_P3

<28> <28>

PCIE_PTX_GLANRX_N3 PCIE_PTX_GLANRX_P3

<30> <30>

PCIE_PRX_WLANTX_N4 PCIE_PRX_WLANTX_P4

<30> <30>

PCIE_PTX_WLANRX_N4 PCIE_PTX_WLANRX_P4

<29> <29>

PCIE_PRX_MMITX_N1 PCIE_PRX_MMITX_P1

<29> <29>

PCIE_PTX_MMIRX_N1 PCIE_PTX_MMIRX_P1

PCIE_PRX_GLANTX_N3 PCIE_PRX_GLANTX_P3

G11 F11

PCIE_PTX_GLANRX_N3 PCIE_PTX_GLANRX_P3

C29 B30

PCIE_PRX_WLANTX_N4 PCIE_PRX_WLANTX_P4

F13 G13

PCIE_PTX_WLANRX_N4 PCIE_PTX_WLANRX_P4

B29 A29

PCIE_PRX_MMITX_N1 PCIE_PRX_MMITX_P1

G17 F17

PCIE_PTX_MMIRX_N1 PCIE_PTX_MMIRX_P1

C30 C31 F15 G15

<31> USB3RN4 <31> USB3RP4

B31 A31

<31> USB3TN4 <31> USB3TP4

+PCH_AUSB3PLL

RC149

1

2 3.01K_0402_1% PCH_PCIE_RCOMP

E15 E13 A27 B27

D

BDW_ULT_DDR3L

@ UC1K

PERN5_L0 PERP5_L0

USB2N0 USB2P0

PETN5_L0 PETP5_L0

USB2N1 USB2P1

PERN5_L1 PERP5_L1

USB2N2 USB2P2

PETN5_L1 PETP5_L1

USB2N3 USB2P3

PERN5_L2 PERP5_L2

USB2N4 USB2P4

PETN5_L2 PETP5_L2

USB2N5 USB2P5

PERN5_L3 PERP5_L3

USB2N6 USB2P6

PETN5_L3 PETP5_L3

USB2N7 USB2P7

PERN3 PERP3 PETN3 PETP3

USB3RN1 USB3RP1 PCIE

USB

PERN4 PERP4

USB3TN1 USB3TP1 USB3RN2 USB3RP2

PETN4 PETP4

USB3TN2 USB3TP2

AN8 AM8

USBP0USBP0+

AR7 AT7

USBP1USBP1+

AR8 AP8

USBP2USBP2+

AR10 AT10

USBP3USBP3+

AM15 AL15

USBP4USBP4+

AM13 AN13

USBP5USBP5+

AP11 AN11

USBP6USBP6+

AR13 AP13

USBP7USBP7+

G20 H20 C33 B34 E18 F18 B33 A33

PCB USBP0- <31> USBP0+ <31>

-----> Ext Port 1

USBP1- <32> USBP1+ <32>

-----> Ext Port 2 charge

USBP2- <30> USBP2+ <30>

-----> WLAN/BT

H12 Entry

USBP3- <31> USBP3+ <31>

-----> Ext Port 3

H14 DSC WWAN

USBP4- <23> USBP4+ <23>

-----> Touch

USBP5- <23> USBP5+ <23>

-----> Camera

USBP6- <27> USBP6+ <27>

-----> USH

H14D_En

NA

USBP7- <30> USBP7+ <30>

-----> WWAN

H14U_En

NA

USB3RN1 USB3RP1

<31> <31>

USB3TN1 USB3TP1

<31> <31>

USB3RN2 USB3RP2

<32> <32>

USB3TN2 USB3TP2

<32> <32>

H12 UMA WWAN

USBRBIAS USBRBIAS RSVD RSVD

PERN2/USB3RN4 PERP2/USB3RP4 PETN2/USB3TN4 PETP2/USB3TP4

AJ10 AJ11 AN10 AM10

NA

H14 UMA WWAN

H15 DSC WWAN

-----> Ext USB3 Port 1

C

H15 UMA WWAN -----> Ext USB3 Port 2 charge

PERN1/USB3RN3 PERP1/USB3RP3 PETN1/USB3TN3 PETP1/USB3TP3

USB2 7

USBRBIAS

H15D_En

NA

H15U_En

NA

+PCH_VCCDSW3_3 OC0/GPIO40 OC1/GPIO41 OC2/GPIO42 OC3/GPIO43

RSVD RSVD PCIE_RCOMP PCIE_IREF

AL3 AT1 AH2 AV3

USB_OC0# USB_OC1# USB_OC2# USB_OC3#

<12,31> -----> <12,32> -----> <12,31> -----> <12>

USB Port0 (JUSB1) USB Port1 (JUSB3) USB Port3 (JUSB2)

+3.3V_ALW_PCH

RPC19 <12>

4 3 2 1

PCH_GPIO9

<7> PCH_SMB_ALERT# <9> PCH_BATLOW#

5 6 7 8

10K_8P4R_5% BDW-ULT-DDR3L_BGA1168 11 OF 19 B

B

USBRBIAS

A

PCIE5

PCIE6

H12 UMA SD card

NA

LOM

WLAN

WIGIG


H12 Entry SD card

NA

LOM

WLAN

WIGIG

NA

H14 DSC SD card

NA

LOM

WLAN

GPU

WIGIG

H14 UMA SD card

NA

LOM

WLAN

WIGIG


H14D_En SD card

NA

LOM

WLAN

GPU

WIGIG

H14U_En SD card

NA

LOM

WLAN

WIGIG

NA

H15 DSC SD card

NA

LOM

WLAN

GPU

WIGIG

H15 UMA SD card

NA

LOM

WLAN

WIGIG


H15D_En SD card

NA

LOM

WLAN

GPU

WIGIG

H15U_En SD card 5

NA

LOM

WLAN

WIGIG

NA 4

1

PCIE2 PCIE3 PCIE4

2

PCIE1

RC152 22.6_0402_1%

PCB

CAD NOTE: Route single-end 50-ohms and max 500-mils length. Avoid routing next to clock pins or under stitching capacitors. Recommended minimum spacing to other signal traces is 15 mils.

A


2

Title

U (6/12) Size

Document Number

Date:


Rev 0.3

LA-A901P Sheet 1

11

of

53

5

4

3

2

1

+PCH_VCCDSW3_3 1 LAN_WAKE# 10K_0402_5% 1 PM_LANPHY_ENABLE 10K_0402_5%

2 RC153 2 @ RC92

+1.05V_VCCST H_THERMTRIP# 2 1K_0402_5%

1 RC25

+3.3V_RUN D

D

2

1

2

1

MPHYP_PWR_EN 100K_0402_5% SIO_EXT_SCI# 100K_0402_5%

RC155 RC156

+3.3V_RUN RPC17 <6> MPCIE_RST# <6,20> HDD_DET# <7,29> MMICLK_REQ#

@

BDW_ULT_DDR3L

UC1J

5 6 7 8

PCH_GPIO76

4 3 2 1

10K_8P4R_5%

<9,36> SIO_EXT_WAKE# <28> PM_LANPHY_ENABLE <27>

TPM_PIRQ#

<28,36> LAN_WAKE# PCH_NFC_RST for Goliad

+PCH_VCCDSW3_3 <29> C

MEDIACARD_IRQ#

+3.3V_ALW_PCH @ T22 PAD~D <23> TOUCH__INTR# <38> MPHYP_PWR_EN <37> KB_DET# @T21 PAD~D <23> 3.3V_CAM_EN# <36> SIO_EXT_SMI# <9> PCH_GPIO46

+3.3V_RUN RPC10 4 3 2 1

5 6 7 8

SLATE_MODE MEDIACARD_RST#

USB_OC0#

<11,31>

AC_PRESENT

<9,36>

<11>

10K_8P4R_5%

<30>

RPC5 4 3 2 1

PCH_GPIO44

5 6 7 8

PCH_GPIO16

PCH_GPIO9 @ T27 PAD~D mSATA_DEVSLP

<20> HDD_DEVSLP <36> SIO_EXT_SCI# <21> SPKR

USB_OC2# <11,31> LANCLK_REQ# <7,28>

PCH_GPIO76 SIO_EXT_WAKE#

P1 AU2 AM7 AD6 Y1 T3 AD5 AN5 AD7 AN3

HOST_ALERT1_R_N PCH_GPIO16 TPM_PIRQ# LAN_WAKE# NFC_IRQ MEDIACARD_RST# PCH_GPIO57 SLATE_MODE PCH_GPIO59 PCH_GPIO44 MEDIACARD_IRQ# DIMM_DET PCH_GPIO49 TOUCH__INTR# MPHYP_PWR_EN KB_DET# PCH_GPIO14 3.3V_CAM_EN# SIO_EXT_SMI#

PCH_GPIO10

SIO_EXT_SCI# SPKR

AG6 AP1 AL4 AT5 AK4 AB6 U4 Y3 P3 Y2 AT3 AH4 AM4 AG5 AG3 AM3 AM2 P2 C4 L2 N5 V2

BMBUSY/GPIO76 GPIO8 LAN_PHY_PWR_CTRL/GPIO12 GPIO15 GPIO16 GPIO17 GPIO24 GPIO27 GPIO28 GPIO26 GPIO56 GPIO57 GPIO58 GPIO59 GPIO44 GPIO47 GPIO48 GPIO49 GPIO50 HSIOPC/GPIO71 GPIO13 GPIO14 GPIO25 GPIO45 GPIO46

U/ MISC

GPIO

SERIAL IO

GPIO9 GPIO10 DEVSLP0/GPIO33 SDIO_POWER_EN/GPIO70 DEVSLP1/GPIO38 DEVSLP2/GPIO39 SPKR/GPIO81

10K_8P4R_5% RPC7 4 3 2 1

KB_DET#

GSPI0_CS/GPIO83 GSPI0_CLK/GPIO84 GSPI0_MISO/GPIO85 GSPI0_MOSI/GPIO86 GSPI1_CS/GPIO87 GSPI1_CLK/GPIO88 GSPI1_MISO/GPIO89 GSPI_MOSI/GPIO90 UART0_RXD/GPIO91 UART0_TXD/GPIO92 UART0_RTS/GPIO93 UART0_CTS/GPIO94 UART1_RXD/GPIO0 UART1_TXD/GPIO1 UART1_RST/GPIO2 UART1_CTS/GPIO3 I2C0_SDA/GPIO4 I2C0_SCL/GPIO5 I2C1_SDA/GPIO6 I2C1_SCL/GPIO7 SDIO_CLK/GPIO64 SDIO_CMD/GPIO65 SDIO_D0/GPIO66 SDIO_D1/GPIO67 SDIO_D2/GPIO68 SDIO_D3/GPIO69

D60 V4 T4 AW15 AF20 AB21

R6 L6 N6 L8 R7 L5 N7 K2 J1 K3 J2 G1 K4 G2 J3 J4 F2 F3 G4 F1 E3 F4 D3 E4 C3 E2

@ 0_0402_5%2

1 RC161

PE#

1

2

1

2

1

2

1

RC160 RC158 RC163 RC164

USB_OC3#

<11>

USB_OC1#

<11,32>

RPC16 4 3 2 1

10K_8P4R_5%

3.3V_TP_EN <10> 3.3V_TS_EN <6,23> 3.3V_HDD_EN <20>

RPC3

SIO_RCIN#

5 6 7 8

<6,35> SATA2_PCIE6_L1 <10> TOUCHPAD_INTR# <9,35,36> CLKRUN#

<7>

4 3 2 1

C

10K_8P4R_5% FFS_INT2 <20> LCD_CBL_DET# <7,23>

RPC4 <7,30>

PCH_GPIO4 PCH_GPIO5 PCH_GPIO6 PCH_GPIO7 PCH_GPIO66 PCH_GPIO67 PCH_GPIO68

2

TOUCH__INTR# 5 6 7 8

<7,30> WLANCLK_REQ# <10> PCH_GPIO80 <10> PCH_GPIO52

GPU_GC6_FB_EN <10> PCH_GPIO85 <6> @ T109 PAD~D

USB#

FFS_INT2 LCD_CBL_DET#

<36>

SIO_RCIN# <36> IRQ_SERIRQ <35,36>

GC6_EVENT#_Q BBS_BIT PCH_GPIO87 3.3V_TP_EN

H_THERMTRIP#

PE# 100K_0402_5% FFS_INT2 100K_0402_5% PCH_GPIO67 10K_0402_5% PCH_GPIO68 10K_0402_5%

<10,27> USH_DET# <7,27> CAM_MIC_CBL_DET#

PCH_GPIO69

WIGIGCLK_REQ#

IRQ_SERIRQ

LESS_DET#

GC6_EVENT#_Q

5 6 7 8

PCH_GPIO6 PCH_GPIO7 PCH_GPIO4 PCH_GPIO5

1 2 3 4

4 3 2 1

10K_8P4R_5% <10,23>

<7>

RPC8


PCH_GPIO57

5 6 7 8

THRMTRIP RCIN/GPIO82 SERIRQ PCH_OPI_RCOMP RSVD RSVD

H_THERMTRIP#_R SIO_RCIN# IRQ_SERIRQ PCH_OPI_COMP

8 7 6 5

10K_8P4R_5%

+3.3V_ALW_PCH +3.3V_RUN

10K_8P4R_5% RPC9

DIMM Detect HIGH LOW

ENABLE DISABLE

1 2

1

TOP-BLOCK SWAP OVERRIDE HIGH LOW(DEFAULT)

+3.3V_RUN

HOST_ALERT1_R_N

TLS CONFIDENTIALITY 1 DIMM 2 DIMM

HIGH LOW(DEFAULT)

ENABLE DISABLE

@ RC180 1K_0402_5%

RC303 10K_0402_5%

@ RC181 1K_0402_5%

2

+3.3V_ALW_PCH DIMM_DET

RC179 1K_0402_5%

PCH_GPIO66

1

1

@ RC171

2

1

2

RC175

4 3 2 1

10K_8P4R_5%

@ RC302 10K_0402_5%

1

2

RC174

5 SIO_EXT_SMI# 6 PCH_GPIO87 7 MEDIACARD_IRQ# 8

B

@ RC176 1K_0402_5%

2

3.3V_CAM_EN# 100K_0402_5% NFC_IRQ 100K_0402_5% MPHYP_PWR_EN 10K_0402_5%

mCARD_PCIE#_SATA

+3.3V_RUN

2

RC245

1

B

+3.3V_RUN

1

1

<6,36>

2

2

TPM_PIRQ# 10K_0402_5% PCH_GPIO59 100K_0402_5%

1

1

2

2 RC247

PCH_OPI_COMP 49.9_0402_1%

1

2 RC178

SPKR

No Reboot on TCO Timer expiration HIGH ENABLE LOW(DEFAULT) DISABLE

A

A


4

3

2

Title

U (7/12) Size

Document Number

Date:


Rev 0.3

LA-A901P Sheet 1

12

of

53

5

4

3

2

1

D

D

CFG STRAPS for U @

CFG0

BDW_ULT_DDR3L

CFG8 CFG9 CFG10

AA62 U63 AA61 U62 CFG_RCOMP

V63 A5 E1 D1 J20 H18 B12

TDI_IREF

RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD RSVD_TP RSVD_TP RSVD_TP RESERVED

RSVD RSVD RSVD PROC_OPI_RCOMP

CFG16 CFG18 CFG17 CFG19

RSVD RSVD

CFG_RCOMP

VSS VSS

RSVD RSVD RSVD

RSVD RSVD RSVD RSVD TD_IREF

AV63 AU63

PAD~D T28@ PAD~D T29@

C63 C62 B43


A51 B51


L60

PAD~D T35@

2

CFG16 CFG18 CFG17 CFG19

CFG4

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

EAR-STALL/NOT STALL RESET SEQUENCE AFTER PCU PLL IS LOCKE CFG0

N60

C

W23 Y22 AY15 PROC_OPI_RCOMP CFG1 AV62 D58 P22 N21 P20 R20

PCH/PCH LESS MODE SELECTION


CFG1 2 RC185 1 RC186

1 2

1:(Default) Normal Operation; No stall 0:Lane Reversed

1

<9> <9> <9> <9>

AC60 AC62 AC63 AA63 AA60 Y62 Y61 Y60 V62 V61 V60 U60 T63 T62 T61 T60

CFG0 CFG1

@ RC184 1K_0402_1%

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

2

C

<9> <9> <9> <9> <9> <9> <9> <9> <9> <9> <9> <9> <9> <9> <9> <9>

@ RC183 1K_0402_1%

1

UC1S

CFG_RCOMP 49.9_0402_1% TDI_IREF 8.2K_0402_1%

PROC_OPI_RCOMP 49.9_0402_1%

1

1:(Default) Normal Operation 0:Lane Reversed

2 RC187

B

B

CFG9

CFG8

CFG4

2

1

1 2

2

2

ALLOW THE USE OF NOA ON LOCKED UNITS 1: Enable(Default): Noa will be disable in locked units and enable in un-locked CFG8 units 0: Enable Noa will be available pegardless of the locking of the unit

RC191 1K_0402_5%

NO SVID PROTOCOL CAPABLE VR CONNECTED 1: VRS SVID protocol are present 0:No VR SVID is present CFG9 The chip will not generate(OR Respond to) SVID activity

@ RC190 1K_0402_1%

SAFE MODE BOOT 1: POWER FEATURES ACTIVATED DURING RESET CFG10 0: POWER FEATURES (ESPECIALLY CLOCK GATINE ARE NOT ACTIVATED

@ RC189 1K_0402_1%

@ RC188 1K_0402_1%

1

1

CFG10

Display Port Presence Strap CFG4

1 : Disabled; No Physical Display Port attached to Embedded Display Port 0 : Enabled; An external Display Port device is connected to the Embedded Display Port

A

A


4

3

2

Title

U (8/12) Size

Document Number

Date:


Rev 0.3

LA-A901P Sheet 1

13

of

53

5

4

3

2

1

D

D

2

1

1 @ RC192

0_0402_5%

BDW_ULT_DDR3L

@ UC1Q DC_TEST_AY2_AW2 AY2 DC_TEST_AY3_AW3 AY3 DC_TEST_AY60 AY60 DC_TEST_AY61_AW61 AY61 DC_TEST_AY62_AW62 AY62 TP_DC_TEST_B2 B2 DC_TEST_A3_B3 B3 DC_TEST_A61_B61 B61 B62 DC_TEST_B62_B63 B63 C1 DC_TEST_C1_C2 C2 C

DAISY_CHAIN_NCTF_AY2 DAISY_CHAIN_NCTF_AY3 DAISY_CHAIN_NCTF_AY60 DAISY_CHAIN_NCTF_AY61 DAISY_CHAIN_NCTF_AY62 DAISY_CHAIN_NCTF_B2 DAISY_CHAIN_NCTF_B3 DAISY_CHAIN_NCTF_B61 DAISY_CHAIN_NCTF_B62 DAISY_CHAIN_NCTF_B63 DAISY_CHAIN_NCTF_C1 DAISY_CHAIN_NCTF_C2

DAISY_CHAIN_NCTF_A3 DAISY_CHAIN_NCTF_A4 DAISY_CHAIN_NCTF_A60 DAISY_CHAIN_NCTF_A61 DAISY_CHAIN_NCTF_A62 DAISY_CHAIN_NCTF_AV1 DAISY_CHAIN_NCTF_AW1 DAISY_CHAIN_NCTF_AW2 DAISY_CHAIN_NCTF_AW3 DAISY_CHAIN_NCTF_AW61 DAISY_CHAIN_NCTF_AW62 DAISY_CHAIN_NCTF_AW63

DC_TEST_A3_B3 DC_TEST_A4

A60 A61 A62 AV1 AW1 AW2 AW3 AW61 AW62 AW63

DC_TEST_A60 DC_TEST_A61_B61 DC_TEST_A62 DC_TEST_AV1 DC_TEST_AW1 DC_TEST_AY2_AW2 DC_TEST_AY3_AW3 DC_TEST_AY61_AW61 DC_TEST_AY62_AW62 DC_TEST_AW63

2

2

0_0402_5% 2 0_0402_5%

1 @ RC193 1 @ RC194

4 C


3 2

0_0402_5%

A3 A4

1 @ RC195

Package Daisy Chain: 1.B2-PKG-C1-PCB-C2-PKG-B3-PCB-A3-PKG-A4 2.A62-PKG-A61-PCB-B61-PKG-B62-PCB-B63-PKG-A60 3.AY60-PKG-AW61-PCB-AY61-PKG-AW62-PCB-AY62-PKG-AW63 4.AW1-PKG-AW3-PCB-AY3-PKG-AW2-PCB-AY2-PKG-AV1

@ UC1R

AT2 AU44 AV44 D15

B

F22 H22 J21

BDW_ULT_DDR3L

RSVD RSVD RSVD RSVD

RSVD RSVD RSVD RSVD

N23 R23 T23 U10 B

RSVD RSVD RSVD RSVD RSVD RSVD RSVD

RSVD RSVD RSVD

AL1 AM11 AP7 AU10 AU15 AW14 AY14


A

A


4

3

2

Title

U (9/12) Size

Document Number

Date:


Rev 0.3

LA-A901P Sheet 1

14

of

53

5

4

3

2

1

ESD Request +1.05V_RUN

+VCCIO_OUT +VCC_CORE 1 @EMC@ CC23

+1.35V_MEM

1

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

2

+VCC_CORE

CC24 100P_0402_50V8J

@ UC1L L59 J58

+1.35V_MEM

H_VR_READY RC201

AH26 AJ31 AJ33 AJ37 AN33 AP43 AR48 AY35 AY40 AY44 AY50

3

VCC

A

4

Y

1 @ CC35

2 2 0.1U_0402_25V6

1

2

RESET_OUT#

NC

5

RC202 1K_0402_5%

+3.3V_ALW UC8 1

+VCC_CORE

H_VCCST_PWRGD

GND VCCSENSE

74AUP1G07GW_TSSOP5

+VCCIO_OUT +VCCIOA_OUT

+1.05V_VCCST <45>

2

RC204 75_0402_1%

1

SVID ALERT

1

VIDSCLK

<9> H_VCCST_PWRGD <45> H_VR_EN <45> H_VR_READY <9>

U_PWR_DEBUG#

H_U_SVIDALRT# RC207

@ T74 @ T75 @ T76 @ T77

PAD~D PAD~D PAD~D PAD~D

1 2

CAD Note: Place the PU resistors close to U RC208close to U 300 - 1500mils

VIDSOUT

VIDSOUT

+1.05V_VCCST

+VCC_CORE

D63 H59 P62 P60 P61 N59 N61 T59 AD60 AD59 AA59 AE60 AC59 AG58 U59 V59 AC22 AE22 AE23 AB57 AD57 AG57 C24 C28 C32

RSVD RSVD

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VCC RSVD RSVD VCC_SENSE RSVD VCCIO_OUT VCCIOA_OUT RSVD RSVD RSVD VIDALERT VIDSCLK VIDSOUT VCCST_PWRGD VR_EN VR_READY

HSW ULT POWER

VSS PWR_DEBUG VSS RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD VCCST VCCST VCCST VCC VCC VCC VCC VCC VCC

C36 C40 C44 C48 C52 C56 E23 E25 E27 E29 E31 E33 E35 E37 E39 E41 E43 E45 E47 E49 E51 E53 E55 E57 F24 F28 F32 F36 F40 F44 F48 F52 F56 G23 G25 G27 G29 G31 G33 G35 G37 G39 G41 G43 G45 G47 G49 G51 G53 G55 G57 H23 J23 K23 K57 L22 M23 M57 P57 U57 W57

C

B

+1.05V_VCCST PJP23

1 2

CC37 1U_0402_6.3V6K

CAD Note: RC209 SHOULD BE PLACED CLOSE TO U A

1

2

PAD-OPEN1x1m

@

1 VCCSENSE

CC36 22U_0603_6.3V6M

VCCSENSE

E63 AB23 A59 E20 AD23 AA23 AE59

BDW_ULT_DDR3L


+1.05V_RUN

2

2

RC209 100_0402_1%

1

VCC_SENSE

+VCC_CORE

F59 N58 AC58

H_U_SVIDALRT# L62 N63 VIDSCLK L63 VIDSOUT H_VCCST_PWRGD B59 H_VR_EN F60 H_VR_READY C59

+1.05V_VCCST RC208 110_0402_1%

SVID DATA

CAD Note: Place the PU resistors close to U RC204 close to U 300 1500mils 2 43_0402_5%

VIDALERT_N

<45>

CC34 10U_0603_6.3V6M

@EMC@

@ RC199 10K_0402_5%

1

1

C

<45>

@ CC33 10U_0603_6.3V6M

2 22U_0603_6.3V6M

+1.05V_VCCST

B

CC32 10U_0603_6.3V6M

@ RC198 10K_0402_5% H_VR_EN 2 1.5K_0402_5%

<45>

D

H_VCCST_PWRGD +1.05V_VCCST

<9,36>

CC31 10U_0603_6.3V6M

+3.3V_RUN

1 @EMC@ CC85

@ CC30 10U_0603_6.3V6M

+1.05V_RUN

CC29 10U_0603_6.3V6M

2 22U_0603_6.3V6M

CC28 2.2U_0402_6.3V6M

2 22U_0603_6.3V6M

1 @EMC@ CC84

CC27 2.2U_0402_6.3V6M

1 @EMC@ CC79

@ CC26 2.2U_0402_6.3V6M

U_PWR_DEBUG#

VDDQ DECOUPLING

+VCC_CORE @ CC25 2.2U_0402_6.3V6M

2

+1.05V_RUN

RC197 150_0402_5%

1

RESISTOR STUFFING OPTIONS ARE PROVIDED FOR TESTING PURPOSES

2

2 22U_0603_6.3V6M

1

0_0603_5%

+1.05V_RUN

D

+1.35V_MEM

1

2

2 @ RC196

A


4

3

2

Title

U (10/12) Size

Document Number

Date:


Rev 0.3

LA-A901P Sheet 1

15

of

53

5

4

3

+1.05V_M +1.05V_MODPHY

2

1

+1.05V_RUN

+1.05V_MODPHY_PCH PJP35

2

1 2

1

1 2

+

2

1 +

2

@EMC@ CC42 330U_2.5V_M

VCCHSIO S0 Iccmax = 1.838A

1

@EMC@ CC41 330U_2.5V_M

+

@ CC39 330U_D3_2.5VY_R6M

CC40 1U_0402_6.3V6K

D

CC44 1U_0402_6.3V6K

@ CC43 1U_0402_6.3V6K

CC40 place near K9; CC44 place near L10 CC43 place near M9

1

2

2

1 PAD-OPEN1x1m

D

+RTC_CELL

LPT LP POWER

DSUS4

AB8 +1.05V_RUN

USB2

AC20 AG16 AG17

1 2

1

2

1 2 1 2

1 1

2

1 2 0_0402_5%

CC73 place near AH11 VCCSUS3_3 S0 Iccmax = 63mA

CC78 1U_0402_6.3V6K

2

1 RC213 @

Reminder below power rail need isolation for layout refer attach file for more detail that from Intel review . +PCH_VCCACLKPLL

0_0402_5%

2

1 2

1 2

CC82 1U_0402_6.3V6K

@ CC80 1U_0402_6.3V6K

CC82 place near A20 VCCACLKPLL S0 Iccmax = 31mA

CC81 100U_1206_6.3V6M

LC5 1 2 2.2UH_LQM2MPN2R2NG0L_30%

1

+1.05V_RUN

2 0_0402_5%

CC80 place near AH10 VCCDSW3_3 S0 Iccmax = 114mA

2

B

+PCH_VCCDSW3_3

2

+3.3V_ALW @ RC217 1

CC77 100U_1206_6.3V6M

+3.3V_ALW_PCH

CC78 place near J18 VCCCLK S0 Iccmax = 200mA

1 RC212 @

0_0402_5%

+PCH_VCC1P05


+3.3V_ALW_PCH

2

+3.3V_ALW

CC72 place near AG16

CC73 1U_0402_6.3V6K

RSVD VCC1_05 VCC1_05

+PCH_RTC_VCCSUS3_3

C

1

SUS OSCILLATOR

2 .47U_0402_10V6K

CC97 place near AH10 intel DG Rev 1.2 , page 500 47.3 Boot Strap Capacitor

@ RC216

2

1

CC69 place near U8

CC72 1U_0402_6.3V6K

1 @ CC97

1

2

1

2013/06/10 refer 6L_WP chnage to float,6/14 change back U8 T9

2

VCCSDIO VCCSDIO

2

SERIAL IO

+PCH_VCCDSW +1.05V_RUN

B

2

+1.5V_RUN

1

+3.3V_ALW_PCH

VCCCLK VCCCLK VCCACLKPLL VCCCLK VCCCLK VCCCLK RSVD RSVD RSVD VCCSUS3_3 VCCSUS3_3


+PCH_VCCDSW3_3

@

1 2 THERMAL SENSOR

J15 K14 K16

1

2

1

1

1

2

2

1

2

1

1

1 2 1

+PCH_VCCACLKPLL

CC70 close to Pin J17 CC71 close to Pin R21

J18 K19 A20 J17 R21 T21 K18 M20 V21 AE20 AE21

CC65 place near AG19

+3.3V_RUN

VCCTS1_5 VCC3_3 VCC3_3

CC69 1U_0402_6.3V6K

2

CC61 CC62 place near AE9

1 5.11_0402_1%

CC66 0.1U_0402_10V7K

+PCH_VCC1P05

CC71 1U_0402_6.3V6K

1

+PCH_VCCDSW

+PCH_VCCDSW 2 RC211

CC65 1U_0402_6.3V6K

GPIO/LPC

+1.05V_M

+3.3V_RUN

+1.05V_RUN

CC70 1U_0402_6.3V6K

2

CORE

+1.05V_RUN

CC59 and CC60 place near J11; CC58 place near AE8

+PCH_VCCDSW_R

VRM

J11 H11 H15 AE8 AF22 AG19 AG20 AE9 AF9 AG8 AD10 AD8

CC60 10U_0603_6.3V6M

VCCSUS3_3 VCCSUS3_3 VCCDSW3_3 VCC3_3 VCC3_3

HDA

VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 DSUSBYP DSUSBYP VCCASW VCCASW VCCASW DSUS1 DSUS1

CC59 1U_0402_6.3V6K

DSUS2

+1.05V_M

CC58 1U_0402_6.3V6K

+PCH_VCCDSW3_3

CC64 place near V8 2013/06/10 refer 6L_WP chnage to +3.3V_M, 6/14 change back CC64 22U_0603_6.3V6M

CC68 1U_0402_6.3V6K

CC67 100U_1206_6.3V6M

1 2 2.2UH_LQM2MPN2R2NG0L_30%

CC68 place near AA21 VCCAPLL S0 Iccmax = 57mA

+3.3V_RUN

AC9 AA9 AH10 V8 W9

VCCHDA

AG14 AG13

USB3

CC62 22U_0603_6.3V6M

CC63 place near AC9 CC63 22U_0603_6.3V6M

+V1.05S_APLLOPI LC3

AH13

+3.3V_ALW_PCH

C

+1.05V_RUN

AH14

DSUS3

CC61 1U_0402_6.3V6K

2

J13

CC57 place near AH14 CC57 0.1U_0402_10V7K

CC56 22U_0603_6.3V6M

CC56 place near B11 VCCSATA3PLL S0 Iccmax = 42mA

CC55 22U_0603_6.3V6M


+3.3V_ALW_PCH

2

+PCH_ASATA3PLL

CC54 place near Y8

1

VCCASW VCCASW +1.05V_MODPHY

+3.3V_M

Y8

@

VCCSPI

2

SPI OPI

AH11 +PCH_RTC_VCCSUS3_3 AG10 AE7 +DRRTC 1 2 CC52 0.1U_0402_10V7K

1

VCCSUS3_3 VCCRTC DRTC

2

1 2

1 2

1 2

RTC

2

RSVD VCCAPLL VCCAPLL

HSIO

@ CC54 0.1U_0402_10V7K

+V1.05S_APLLOPI

Y20 AA21 W21

VCCHSIO VCCHSIO VCCHSIO VCC1_05 VCC1_05 VCCUSB3PLL VCCSATA3PLL

CC50 1U_0402_6.3V6K

@ CC53 1U_0402_6.3V6K

CC47 22U_0603_6.3V6M

+PCH_AUSB3PLL +PCH_ASATA3PLL

K9 L10 M9 N8 P9 B18 B11

CC49 0.1U_0402_10V7K

+1.05V_MODPHY_PCH

+1.05V_RUN CC51 22U_0603_6.3V6M

CC47 place near B18 VCCUSB3PLL S0 Iccmax = 41mA

UC1M

CC48 0.1U_0402_10V7K


BDW_ULT_DDR3L

@

+PCH_AUSB3PLL

1

CC48,CC49, CC50 place near AG10 +1.05V_MODPHY

A

A


4

3

2

Title

U (11/12) Size

Document Number

Date:


Rev 0.3

LA-A901P Sheet 1

16

of

53

5

4

3

2

1

D

D

@ UC1N A11 A14 A18 A24 A28 A32 A36 A40 A44 A48 A52 A56 AA1 AA58 AB10 AB20 AB22 AB7 AC61 AD21 AD3 AD63 AE10 AE5 AE58 AF11 AF12 AF14 AF15 AF17 AF18 AG1 AG11 AG21 AG23 AG60 AG61 AG62 AG63 AH17 AH19 AH20 AH22 AH24 AH28 AH30 AH32 AH34 AH36 AH38 AH40 AH42 AH44 AH49 AH51 AH53 AH55 AH57 AJ13 AJ14 AJ23 AJ25 AJ27 AJ29

C

B

BDW_ULT_DDR3L

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

@ UC1O VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AJ35 AJ39 AJ41 AJ43 AJ45 AJ47 AJ50 AJ52 AJ54 AJ56 AJ58 AJ60 AJ63 AK23 AK3 AK52 AL10 AL13 AL17 AL20 AL22 AL23 AL26 AL29 AL31 AL33 AL36 AL39 AL40 AL45 AL46 AL51 AL52 AL54 AL57 AL60 AL61 AM1 AM17 AM23 AM31 AM52 AN17 AN23 AN31 AN32 AN35 AN36 AN39 AN40 AN42 AN43 AN45 AN46 AN48 AN49 AN51 AN52 AN60 AN63 AN7 AP10 AP17 AP20

AP22 AP23 AP26 AP29 AP3 AP31 AP38 AP39 AP48 AP52 AP54 AP57 AR11 AR15 AR17 AR23 AR31 AR33 AR39 AR43 AR49 AR5 AR52 AT13 AT35 AT37 AT40 AT42 AT43 AT46 AT49 AT61 AT62 AT63 AU1 AU16 AU18 AU20 AU22 AU24 AU26 AU28 AU30 AU33 AU51 AU53 AU55 AU57 AU59 AV14 AV16 AV20 AV24 AV28 AV33 AV34 AV36 AV39 AV41 AV43 AV46 AV49 AV51 AV55

BDW_ULT_DDR3L



AV59 AV8 AW16 AW24 AW33 AW35 AW37 AW4 AW40 AW42 AW44 AW47 AW50 AW51 AW59 AW60 AY11 AY16 AY18 AY22 AY24 AY26 AY30 AY33 AY4 AY51 AY53 AY57 AY59 AY6 B20 B24 B26 B28 B32 B36 B4 B40 B44 B48 B52 B56 B60 C11 C14 C18 C20 C25 C27 C38 C39 C57 D12 D14 D18 D2 D21 D23 D25 D26 D27 D29 D30 D31

BDW_ULT_DDR3L

@ UC1P D33 D34 D35 D37 D38 D39 D41 D42 D43 D45 D46 D47 D49 D5 D50 D51 D53 D54 D55 D57 D59 D62 D8 E11 E17 F20 F26 F30 F34 F38 F42 F46 F50 F54 F58 F61 G18 G22 G3 G5 G6 G8 H13

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS_SENSE VSS

H17 H57 J10 J22 J59 J63 K1 K12 L13 L15 L17 L18 L20 L58 L61 L7 M22 N10 N3 P59 P63 R10 R22 R8 T1 T58 U20 U22 U61 U9 V10 V3 V7 W20 W22 Y10 Y59 Y63

C

V58 AH46 V23 E62 AH16

VSSSENSE

<45>

BDW-ULT-DDR3L_BGA1168 16 OF 19 B

VSSSENSE RC218


1

2 100_0402_1%

CAD Note: RC218 SHOULD BE PLACED CLOSE TO U


A

A


4

3

2

Title

U (12/12) Size

Document Number

Date:


Rev 0.3

LA-A901P Sheet 1

17

of

53

5

3

DDR_A_DQS#[0..7]

M_CLK_DDR0 M_CLK_DDR#0

<8>

DDR_A_BS0

<8> DDR_A_WE# <8> DDR_A_CAS#

Layout Note: Place near JDIMM1.203,204

<8>

DDR_CS1_DIMMA#

DDR_A_MA10 DDR_A_BS0 DDR_A_WE# DDR_A_CAS# DDR_A_MA13 DDR_CS1_DIMMA#

DDR_A_D2 DDR_A_D6

1 2

1 2

1 2

1 2

2

DDR_A_D17 DDR_A_D16 DDR_A_D36 DDR_A_D33


DDR_A_D60 DDR_A_D61

2 0_0402_5%

+0.675V_DDR_VTT

2

CD32 0.1U_0402_25V6

A

@ CD31 2.2U_0402_6.3V6M

1

2

1

1 @ RD16

0_0402_5% +3.3V_RUN

2

1 @ RD15

205 207

GND1 BOSS1

GND2 BOSS2

2 2_0402_1%

1 2 2

1 M_CLK_DDR1 M_CLK_DDR#1

DDR_A_BS1 DDR_A_RAS#

1

<8> <8>

DDR_A_BS1 <8> DDR_A_RAS# <8>

DDR_CS0_DIMMA# M_ODT0

DDR_CS0_DIMMA#

<8>

M_ODT1 +SM_VREF_CA_DIMM

DDR_A_D5 DDR_A_D4

DDR_A_D3 DDR_A_D7

+5V_ALW

DDR_A_D18 DDR_A_D19 DDR_A_DQS#2 DDR_A_DQS2 DDR_A_D22 DDR_A_D23 DDR_A_D37 DDR_A_D32

DDR3L SODIMM ODT GENERATION

1

3

1 RD10 1 RD11 1 RD12 1 RD13

0.675V_DDR_VTT_ON


B

+1.35V_MEM QD1 L2N7002WT1G_SC-70-3 M_ODT0 2 66.5_0402_1% M_ODT1 2 66.5_0402_1% 2 66.5_0402_1% 2 66.5_0402_1%

M_ODT2

<19>

M_ODT3

<19>

@ RD14 2M_0402_5%

DDR_A_DQS#4 DDR_A_DQS4


RD9 220K_0402_5%

DDR_A_D21 DDR_A_D20

CD29 10U_0603_6.3V6M

CD28 10U_0603_6.3V6M

CD27 0.1U_0402_25V6

CD26 0.1U_0402_25V6

CD25 0.1U_0402_25V6

CD24 0.1U_0402_25V6

1

+0.675V_DDR_VTT

DDR_A_MA2 DDR_A_MA0

CD23 2.2U_0402_6.3V6M


1

DDR_A_MA6 DDR_A_MA4

C

+SM_VREF_DQ0

RD5

DDR_A_MA11 DDR_A_MA7

CD22 0.1U_0402_25V6

DDR_A_D0 DDR_A_D1

+DIMM1_VREF_DQ

<8>

RD7 24.9_0402_1%

<8> <8>


DDR_CKE1_DIMMA


2

DDR_A_MA3 DDR_A_MA1

DDR_CKE1_DIMMA

1

DDR_A_MA8 DDR_A_MA5

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

2


CKE1 VDD A15 A14 VDD A11 A7 VDD A6 A4 VDD A2 A0 VDD CK1 CK1# VDD BA1 RAS# VDD S0# ODT0 VDD ODT1 NC VDD VREF_CA VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS EVENT# SDA SCL VTT

1

DDR_A_BS2

CKE0 VDD NC BA2 VDD A12/BC# A9 VDD A8 A5 VDD A3 A1 VDD CK0 CK0# VDD A10/AP BA0 VDD WE# CAS# VDD A13 S1# VDD TEST VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SA0 VDDSPD SA1 VTT

2

DDR_A_BS2

73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203

+1.35V_MEM

DDR_A_D54 DDR_A_D55

S

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

<8>

DDR_CKE0_DIMMA

CAD NOTE PLACE THE CAP NEAR TO DIMM RESET PIN


CD21 0.022U_0402_16V7K

2

DDR_CKE0_DIMMA

DDR_A_D52 DDR_A_D53

RD6 1.8K_0402_1%

+

CD20 330U_D2_2V_Y

CD19 10U_0603_6.3V6M

CD18 10U_0603_6.3V6M

CD17 10U_0603_6.3V6M

@ CD16 10U_0603_6.3V6M

CD15 10U_0603_6.3V6M

CD14 10U_0603_6.3V6M

@ CD13 10U_0603_6.3V6M

CD12 10U_0603_6.3V6M

1

<8>

<9,19>

DDR_A_D42 DDR_A_D46

D

+1.35V_MEM C

DDR_A_D45 DDR_A_D40

DDR3_DRAMRST#

RD4 1.8K_0402_1%

DDR_A_D49 DDR_A_D48

D

DDR3_DRAMRST#

DDR_A_D27 DDR_A_D26

2 G

DDR_A_D51 DDR_A_D50

DDR3_DRAMRST#

1

DDR_A_D43 DDR_A_D47

DDR_A_D25 DDR_A_D24

2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

2


CD11 1U_0402_6.3V6K

CD10 1U_0402_6.3V6K

CD4 1U_0402_6.3V6K

CD9 1U_0402_6.3V6K

CD8 1U_0402_6.3V6K

CD3 1U_0402_6.3V6K

CD2 1U_0402_6.3V6K

CD7 1U_0402_6.3V6K

1

DDR_A_D44 DDR_A_D41

DDR_A_D15 DDR_A_D11

2

+1.35V_MEM

+1.35V_MEM DDR_A_DQS#1 DDR_A_DQS1

@ CD6 0.1U_0402_25V6

DDR_A_D30 DDR_A_D31

DDR_A_D9 DDR_A_D12

1


1

+1.35V_MEM

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

1

DDR_A_D29 DDR_A_D28

VSS DQ4 DQ5 VSS DQS0# DQS0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 RESET# VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS

2

DDR_A_D14 DDR_A_D10

VREF_DQ VSS DQ0 DQ1 VSS DM0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 VSS DQ26 DQ27 VSS

1

1 2

DDR_A_D13 DDR_A_D8

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71

RD2 470_0402_5%

CD1 0.1U_0402_25V6

CD5 2.2U_0402_6.3V6M

Note: Check voltage tolerance of VREF_DQ at the DIMM socket

Layout Note: Place near JDIMM1

2

1

JDIMM1

DDR_A_MA[0..15]

D

B

H=4mm Reverse Type

+1.35V_MEM

1

<8>

+DIMM1_VREF_DQ

2

DDR_A_DQS[0..7]

1

DDR_A_D[0..63]

<8>

2

2

<8>

2

<8>

4


+1.35V_MEM

DDR_A_D56 DDR_A_D57

UD1

1 <9> DDR_XDP_WAN_SMBDAT DDR_XDP_WAN_SMBCLK

DDR_PG_CTRL

<7,9,19,20> <7,9,19,20>

2 3

+0.675V_DDR_VTT

NC

VCC

A Y

5 4

1 @ CD30

2 0.1U_0402_25V6

0.675V_DDR_VTT_ON

0.675V_DDR_VTT_ON

<42>

GND 74AUP1G07GW_TSSOP5

206 208

A

BELLW_80001-1021 CONN@


Title

DDR3L Size

4

3

2

Rev 0.3

LA-A901P Date:

5


Sheet 1

18

of

53

5

4

3

DDR_B_MA10 DDR_B_BS0

DDR_B_BS0

<8> DDR_B_WE# <8> DDR_B_CAS# <8>

DDR_B_MA13 DDR_CS3_DIMMB#

DDR_CS3_DIMMB#

Layout Note: Place near JDIMM2.203,204

DDR_B_D3 DDR_B_D7

B

DDR_B_D21 DDR_B_D20

DDR_B_D22 DDR_B_D23

+0.675V_DDR_VTT

1 2

1 2

1 2

1 2

1 2

2

CD62 10U_0603_6.3V6M

CD61 10U_0603_6.3V6M

CD60 0.1U_0402_25V6

CD59 0.1U_0402_25V6

CD58 0.1U_0402_25V6

CD57 0.1U_0402_25V6

1

DDR_B_D36 DDR_B_D33 DDR_B_DQS#4 DDR_B_DQS4 DDR_B_D35 DDR_B_D39 DDR_B_D52 DDR_B_D49

DDR_B_D48 DDR_B_D53 +3.3V_RUN +3.3V_RUN

1 2

2

CD64 0.1U_0402_25V6

@ CD63 2.2U_0402_6.3V6M

A

+0.675V_DDR_VTT @ RD28 0_0402_5%

2

0_0402_5%

1

1

1

2 @ RD27

205 207

GND1 BOSS1

GND2 BOSS2

1 2 1 2

1 2 1 2

DDR_B_MA11 DDR_B_MA7 +DIMM2_VREF_DQ

DDR_B_MA6 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0

+SM_VREF_DQ1

1

2

RD23 M_CLK_DDR3 M_CLK_DDR#3

DDR_B_BS1 DDR_B_RAS#

<8> <8>

DDR_B_BS1 <8> DDR_B_RAS# <8>

DDR_CS2_DIMMB# M_ODT2

DDR_CS2_DIMMB# M_ODT2 <18> M_ODT3

<18>

2_0402_1%

1


<8>

+SM_VREF_CA_DIMM

DDR_B_D5 DDR_B_D0

DDR_B_D2 DDR_B_D6

CD56 2.2U_0402_6.3V6M

DDR_B_DQS#0 DDR_B_DQS0

C

+1.35V_MEM

CD55 0.1U_0402_25V6

DDR_B_D4 DDR_B_D1

<8>

RD25 24.9_0402_1%

DDR_B_WE# DDR_B_CAS#

DDR_CKE3_DIMMB

DDR_B_MA15 DDR_B_MA14

2

<8>

DDR_CKE3_DIMMB

1



DDR_B_D63 DDR_B_D62

2

1 2

1 2

1 2

1 2

1 2

1 2

1

1 2

<8> <8>


CD54 0.022U_0402_16V7K

+

DDR_B_MA3 DDR_B_MA1

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

2_0402_1%

RD24 1.8K_0402_1%

2

DDR_B_MA8 DDR_B_MA5 CD53 330U_D2_2V_Y

CD52 10U_0603_6.3V6M

CD51 10U_0603_6.3V6M

CD50 10U_0603_6.3V6M

CD49 10U_0603_6.3V6M

CD48 10U_0603_6.3V6M

@ CD47 10U_0603_6.3V6M

2

DDR_B_MA12 DDR_B_MA9 @ CD46 10U_0603_6.3V6M

CD45 10U_0603_6.3V6M

1

+1.35V_MEM

CKE1 VDD A15 A14 VDD A11 A7 VDD A6 A4 VDD A2 A0 VDD CK1 CK1# VDD BA1 RAS# VDD S0# ODT0 VDD ODT1 NC VDD VREF_CA VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS EVENT# SDA SCL VTT

CAD NOTE PLACE THE CAP NEAR TO DIMM RESET PIN

1

DDR_B_BS2

DDR_B_BS2

CKE0 VDD NC BA2 VDD A12/BC# A9 VDD A8 A5 VDD A3 A1 VDD CK0 CK0# VDD A10/AP BA0 VDD WE# CAS# VDD A13 S1# VDD TEST VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SA0 VDDSPD SA1 VTT

2

RD22 1.8K_0402_1%

<8>

73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203

1

DDR_B_D47 DDR_B_D43 DDR_B_D61 DDR_B_D60

+SM_VREF_CA

RD19

2

DDR_CKE2_DIMMB

DDR_CKE2_DIMMB

+SM_VREF_CA_DIMM

1

<8> C

DDR_B_D45 DDR_B_D44

<9,18>

2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

CD44 1U_0402_6.3V6K

CD43 1U_0402_6.3V6K

CD42 1U_0402_6.3V6K

CD41 1U_0402_6.3V6K

CD40 1U_0402_6.3V6K

CD39 1U_0402_6.3V6K

CD38 1U_0402_6.3V6K

CD37 1U_0402_6.3V6K

DDR_B_D59 DDR_B_D58

DDR3_DRAMRST#

DDR_B_D30 DDR_B_D31

RD21 24.9_0402_1%

DDR_B_D56 DDR_B_D57

DDR3_DRAMRST#

1

DDR_B_D46 DDR_B_D42

+1.35V_MEM

DDR_B_D25 DDR_B_D24

RD20 1.8K_0402_1%


+1.35V_MEM

CD36 0.022U_0402_16V7K

DDR_B_D40 DDR_B_D41

D

DDR_B_D13 DDR_B_D15

2

DDR_B_D26 DDR_B_D27


@ CD35 0.1U_0402_25V6

Layout Note: Place near JDIMM2

DDR_B_D12 DDR_B_D9

1


2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

RD18 1.8K_0402_1%

DDR_B_D28 DDR_B_D29

VSS DQ4 DQ5 VSS DQS0# DQS0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 RESET# VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS

2

DDR_B_D10 DDR_B_D11

VREF_DQ VSS DQ0 DQ1 VSS DM0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 VSS DQ26 DQ27 VSS

1

1

DDR_B_D8 DDR_B_D14

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71

2

2

DDR_B_MA[0..15]

2

Note: Check voltage tolerance of VREF_DQ at the DIMM socket

1

DDR_B_DQS[0..7]

CD34 0.1U_0402_25V6

<8>

+1.35V_MEM JDIMM2

CD33 2.2U_0402_6.3V6M

DDR_B_D[0..63]

<8>

D

+1.35V_MEM

DDR_B_DQS#[0..7]

<8>

1

H=4mm Reverse Type

+DIMM2_VREF_DQ <8>

2

DDR_B_D16 DDR_B_D17

B

DDR_B_DQS#2 DDR_B_DQS2 DDR_B_D19 DDR_B_D18 DDR_B_D37 DDR_B_D32

DDR_B_D34 DDR_B_D38 DDR_B_D51 DDR_B_D55 DDR_B_DQS#6 DDR_B_DQS6 DDR_B_D54 DDR_B_D50

DDR_XDP_WAN_SMBDAT <7,9,18,20> DDR_XDP_WAN_SMBCLK <7,9,18,20> +0.675V_DDR_VTT

206 208 A

BELLW_80001-1021 CONN@


Title

DDR3L Size

4

3

2

Rev 0.3

LA-A901P Date:

5


Sheet 1

19

of

53

3

2

PH

PD (RN11)

PD (RN9)

PD (RN25)

NC (IPU)

PD (RN13)

PD

NC

NC

(RN16)

PD (RN23)

NC

PH

NC

PD

(RN19)

PD

(RN11)

PH

(RN8)

(RN25)

(RN22)

A_EM

1

2

B_EM

C

Free Fall Sensor UN1

LNG3DM 1 14

Main

Pericom

2nd

TI

0 NC 1

3dB 6dB 9dB

3dB 6dB 9dB

0 NC 1

1.5dB

0 NC 1

7dB 0dB 14dB

7dB 0dB 14dB

0 NC 1

0dB -6dB -3dB

A_EQ

B_EQ

2.4dB 7.4dB 14.4dB 12.2dB 9.4dB 13.3dB 6.2dB 11.2dB 5dB

2.4dB 7.4dB 14.4dB 12.2dB 9.4dB 13.3dB 6.2dB 11.2dB 5dB

0dB

0dB

<6,10>

1.5dB

<7,9,18,19> <7,9,18,19>

0dB -6dB -3dB

EQ1

A_EM

HDD_FALL_INT

11 9

FFS_INT2

7 6 4

DDR_XDP_WAN_SMBDAT DDR_XDP_WAN_SMBCLK

8

RES RES RES RES

VDD_IO VDD INT 1 INT 2

GND GND SDO/SA0 SDA / SDI / SDO SCL/SPC NC CS NC

10 13 15 16 5 12

2 3

LNG3DMTR_LGA16_3X3 +3.3V_HDD 1

EQ2

1 3

1 2 6

1

DDR_XDP_WAN_SMBDAT 2.2K_0402_5% 2 DDR_XDP_WAN_SMBCLK 2.2K_0402_5%

1 RN3 1

B_EQ

2

1 2

2 1

2

+3.3V_RUN

RN4

A_EQ

2

1 2

1 2

1 2

1 2 1

2 1

2 1

2

+3.3V_RUN

C

Parade PS8527C

D

PD

(RN22)

1

NC

2

NC

1

PD

2

(RN25)

CN2 0.1U_0402_25V6

(IPU)

CN1 10U_0603_6.3V6M

(RN11)

1

PIN19

@ RN25 4.7K_0402_5%

HDD_B_EQ

PIN18

@ RN23 4.7K_0402_5%

HDD_A_EQ2

PIN17

@ RN21 4.7K_0402_5%

HDD_A_EQ

PIN16

@ RN19 4.99K_0402_1%

DEW1

PIN13

RN16 4.7K_0402_5%

NC (IPU)

TI SN75LV601

NC

2

HDD_B_EQ2

@ RN13 4.7K_0402_5%

PD

2

HDD_A_EQ2

HDD_B_EQ2

PIN9

FFS_INT2

FFS_INT2

1

12 SATA_PRX_DTX_N1_RP 11 SATA_PRX_DTX_P1_RP

RN11 4.7K_0402_5%

NC

Pericom PI3EQX6741ST

PIN8

2

<12>

DEW1

GND

HDD_B_PRE HDD_A_PRE

1

DEW2

@ RN9 4.7K_0402_5%

DEW2

1

HDD_B_EQ

15 SATA_PTX_DRX_P1_RP 14 SATA_PTX_DRX_N1_RP

PI3EQX6741STZDEX_TQFN20_4X4

PIN6

2

HDD_A_EQ

5 4

HDD_B_EQ2 HDD_B_EQ HDD_B_PRE HDD_A_EQ2

FFS_INT2_Q QN1B DMN66D0LDW-7_SOT363-6

BIBI+

HDD_B_PRE 13 19 8 18

@ RN1 100K_0402_5%

BOBO+

HDD_A_PRE

QN1A DMN66D0LDW-7_SOT363-6

AO+ AO-

+3.3V_RUN RN2 100K_0402_5%

21

AI+ AI-

@ RN24 4.7K_0402_5%

SATA_PRX_DTX_N1_C 4 SATA_PRX_DTX_P1_C 5

2 0.01U_0402_16V7K 2 0.01U_0402_16V7K

TDet_B# TDet_A# A_EQ B_EQ A_EM B_EM EN TDeT_EN

10 20

+5V_HDD

@ RN22 4.7K_0402_5%

CN25 1 CN26 1

VDD VDD

@ RN20 4.7K_0402_5%

SATA_PRX_DTX_N1 SATA_PRX_DTX_P1

SATA_PTX_DRX_P1_C 1 SATA_PTX_DRX_N1_C 2

2 0.01U_0402_16V7K 2 0.01U_0402_16V7K

NC NC

@ RN18 4.7K_0402_5%

<6> <6>

CN23 1 CN30 1

HDD_A_EQ HDD_A_PRE

3 17 9 7

@ RN14 4.7K_0402_5%

SATA_PTX_DRX_P1 SATA_PTX_DRX_N1

6 16

@ RN12 4.7K_0402_5%

<6> <6>

DEW2 DEW1

@ RN10 4.7K_0402_5%

D

2

@ RN8 4.7K_0402_5%

2 UN2

1

CN24 0.1U_0402_25V6

1

CN29 0.01U_0402_16V7K

SATA Repeater

2

+3.3V_HDD

1

+3.3V_HDD

1

2

4

1

5

B_EM

2

@ RN5

HDD_DEVSLP 10K_0402_5%

(M = VDD/2)

0 0 0 M M M 1 1 1

B

3rd

Parade

M 0 1 M 0 1 M 0 1

0 M 1

0dB -3.5dB -1.5dB

0dB -3.5dB -1.5dB

1 0.01U_0402_16V7K SATA_PTX_DRX_P1_RP_C 1 0.01U_0402_16V7K SATA_PTX_DRX_N1_RP_C

SATA_PRX_DTX_N1_RP CN18 2 SATA_PRX_DTX_P1_RP CN17 2

1 0.01U_0402_16V7K SATA_PRX_DTX_N1_RP_C 1 0.01U_0402_16V7K SATA_PRX_DTX_P1_RP_C PJP4 +3.3V_HDD 1 2

+3.3V_RUN

HDD_DEVSLP

<6,12>

HDD_DET#

PJP5 +5V_HDD

+3.3V_HDD

+5V_RUN

1

+5V_HDD

2

1

VIN

VOUT VOUT

7

PJP7

+3.3V_RUN_UN3

1

8 2

1 2

5

@ CN4 470P_0402_50V7K

2

CT

GND GND

5 9

1

6 1

@ RN7 10K_0402_5%

VBIAS

TPS22967DSGR_SON8_2X2

CN3 0.1U_0402_10V7K

4

+5V_ALW

+3.3V_HDD

STARC_115B20-000000-G2-R CONN@

1 2

1 2

1

PAD-OPEN1x1m

3.3V_HDD_EN

A

2

2

1 2

VIN

2

2

ON

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 G1 G2 G3 G4

@

1

+3.3V_RUN

FFS_INT2_Q

CN16 0.1U_0402_25V6

@ RN6 10K_0402_5%

@ CN15 0.1U_0402_25V6

@ UN3 3

CN14 0.1U_0402_25V6

+3.3V_RUN_UN3

CN13 1000P_0402_50V7K

+3.3V_RUN

3.3V_HDD_EN

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

PAD-OPEN1x1m <12>

PAD-OPEN1x1m

<12>

B

JSATA1 SATA_PTX_DRX_P1_RP CN19 2 SATA_PTX_DRX_N1_RP CN20 2

A

Place near HDD CONN


For Lite-On dirty shutdown TPS22965 EOL change to TPS22967

4


2

Title

HDD CONN Size

Document Number

Date:


Rev 0.3

LA-A901P Sheet 1

20

of

53

1

24

DAI_DI

SPK-OUT-L+ SPK-OUT-LI2S_MCLK SPK-OUT-R+ SPK-OUT-R-

I2S_SCLK I2S_DOUT

PCBEEP

I2S_LRCK GPIO0/DMIC-CLK GPIO1/DMIC-DATA12

I2S_DIN

SPDIF-OUT/DMIC-DATA34/GPIO2

20

2

1

49

AUD_PC_BEEP

2 4

DMIC_CLK_L DMIC1

EAPD+PD

CBP VEE VREF

LDO1-CAP LDO2-CAP LDO3-CAP

MIC1-VREFO AVSS1 AVSS2

GND

35 36

30 26 37

1

2

MIC1_R

CA44 1

2 1

4.7U_0603_6.3V6K 2

2

2

2

2

+3.3V_RUN_AUDIO

PAD-OPEN1x1m

HP-Out-Right

Nokia-MIC

HP-Out-Left

iPhone-MIC

AUD_HP_OUT_R

4.7U_0603_6.3V6K

2 +3.3V_RUN_AUDIO 1

1

2

RA1 10K_0402_5%

RING2 EMC@ LA10 1 AUD_HP_OUT_L EMC@ LA2 1

5 DOCK_MIC_DET QA3B DMN66D0LDW-7_SOT363-6

+5V_RUN_AUDIO

PJP10 1

+3.3V_RUN

AUD_HP_OUT_L

2

2

PAD-OPEN1X2m

2

1

1 2

CA43 1

+3.3V_RUN_AUDIO

3 4

1

MIC1_L

1

1 2

3

QA1 L2N7002WT1G_SC-70-3 1 2 6

1 2

0_0402_5%

1

PJP9 1

+5V_RUN

2 BLM15PX330SN1D_2P 2 BLM15BD601SN1D_2P

@EMC@ CA13 680P_0402_50V7K

DOCK_HP_DET

0_0402_5%

1 RA37 @

place close to RA40 pin2

PAD-OPEN1x2m

+3.3V_RUN_AUDIO

RA26 100K_0402_5%

2 QA3A DMN66D0LDW-7_SOT363-6

RA27 200K_0402_5%

Global Headset

Universal Jack JHP1

RING2_R AUD_HP_OUT_L1

3 1

<35>

Normal Open

5

A

SLEEVE AUD_HP_NB_SENSE

6

+RTC_CELL

2

2

1

3 1

2

3

2

3 1

1

2 QA2A DMN66D0LDW-7_SOT363-6 1 6

G

7

SINGA_2SJ3080-023111F CONN@ 1

2

@EMC@ CA12 680P_0402_50V7K

EMC@ DA3

100K_0402_5%

AUD_NB_MUTE#

Realtek Prevent the Noise from Combo Jack while system entry into S3 / S4 /S5

2

2

EMC@ DA2

AZ5123-02S.R7G_SOT23-3

2

2

EMC@ DA1

RA2

DMIC1 DMIC_CLK1

2

1

L03ESDL5V0CC3-2_SOT23-3

6 5 4

2

1

AZ5123-02S.R7G_SOT23-3

GND VCC LEFT/RIGHT DATA GND CLOCK SPM1437HM4H-6_6P

5

1

EMC@ CA4 680P_0402_50V7K

1 2 3

1

2 4 @EMC@ CA3 220P_0402_50V7K

MIC1

AUD_HP_OUT_R1 SLEEVE_R @EMC@ CA2 220P_0402_50V7K

+3.3V_RUN

2 BLM15BD601SN1D_2P 2 BLM15PX330SN1D_2P

EMC@ CA1 680P_0402_50V7K

Digital Mic

RA21 100K_0402_5%

1

AUD_HP_OUT_R EMC@ LA3 1 SLEEVE EMC@ LA11 1

QA2B DMN66D0LDW-7_SOT363-6 4 3

<35>

RA29 100K_0402_5%

A

RA28 100K_0402_5%

+3.3V_RUN_AUDIO

2 100K_0402_5%

1

place close to UA1 pin2

DA5 RB751S40T1G_SOD523-2

1 RA38

2

2 1 1U_0603_10V6K 2 1 1 1U_0603_10V6K CA49 2 CA35 2.2U_0402_6.3V6M +MIC1_VREF_OUT

RA25 4.7K_0402_5% DA4 RB751S40T1G_SOD523-2

AUD_SENSE_B

1

DMIC_CLK1

ALC3235-CG_MQFN48_6X6

2

2

<36>

<23>

0_0402_5%

1 RA36 @

BEEP <23>

CA29 34 25

place at AGND and DGND plane 1 RA35 @

<12>

Place CA29 close to Codec

<35>

Add for solve pop noise and detect issue

2 DMIC0

DMIC_CLK0

SPKR

DMIC_CLK0

MIC1-R(PORT-B-R)

PJP6

Place closely to Pin 14 for DOCK only

1

47

2 1K_0402_5% 2 1K_0402_5%

MIC1-L(PORT-B-L)

RA24 4.7K_0402_5%

@ CA41 0.1U_0402_25V6

S

AUD_HP_NB_SENSE

1

1 1 0.1U_0402_25V6 RA12 1 1 0.1U_0402_25V6 RA13 DMIC_CLK0 1 2 2 33_0402_5% DMIC_CLK1 EMC@ RA141 EMC@ RA40 33_0402_5%

D

2 G

2

1

12

RA6

+VREFOUT 2 CA27 2 CA28

2

2

1 2

CA53 4.7U_0603_6.3V6K

CA52 4.7U_0603_6.3V6K

AUD_SENSE_A

CA51 4.7U_0603_6.3V6K

Verb table configures as 1 JD mode with internal 47K pull high to save external rBOM.

1

21 39 7 RA44 100K_0402_5%

2

RA18

48

2

+3.3V_RUN_AUDIO

2 10K_0402_5%

1

1

1

2

AUD_NB_MUTE#

AUD_NB_MUTE#

INT_SPK_R+ INT_SPK_R-

2

CA30 22P_0402_50V8J

<35>

45 44

B

RA5

CA54 22P_0402_50V8J

1

19

MIC1_R

CBN CA31 1U_0603_10V6K

@EMC@ CA33 10P_0402_50V8J

BCLK: Audio serial data bus bit clock input/output LRCK: Audio serial data bus word clock input/output

MIC1_L

42 43

2

1

RESET#

31 33 32

1 RING2 2.2K_0402_5% 1 SLEEVE 2.2K_0402_5%

@

MIC-CAP HPOUT-L(PORT-A-L) HPOUT-R(PORT-A-R)

+VREFOUT SLEEVE/RING2 please keep 40 mils trace width +VREFOUT 2 10U_0603_6.3V6M AUD_HP_OUT_L 1 2 1 2 24.9_0402_1% AUD_HP_OUT_R 24.9_0402_1% AUD_HP_OUT_L/ AUD_HP_OUT_Rplease keep 15 mils trace width

2

SDATA-IN

+3.3V_RUN_AUDIO

RING2 SLEEVE 1 CA25 AUD_OUT_L AUD_OUT_R RA7 RA8 INT_SPK_L+ INT_SPK_L-

2

1

18

SYNC

1

@EMC@

17

LINE1-L(PORT-C-L)/RING2 LINE1-R(PORT-C-R)/SLEEVE LINE1-VREFO

2

place close to pin46

2

16

SDATA-OUT

1 @ RA45

28 29 23

1

@EMC@

15

DAI_LRCK#

<34>

2

1 2 2

BCLK

+5V_RUN_PVDD

1

DAI_DO#

<34>

11

AUD_SENSE_A AUD_SENSE_B 2 0_0402_5%

2


CA26 1U_0603_10V4Z

@EMC@ RA17 33_0402_5%

<34>

DAI_BCLK#

8

PCH_AZ_CODEC_RST#

I2S_MCLK 22_0402_5% 2 I2S_BCLK 22_0402_5% 2 I2S_DO Place RA32 close to codec 33_0402_5%

1 EMC@ RA30 1 EMC@ RA31 1 RA32

DAI_12MHZ#

<34> PCH_AZ_CODEC_BITCLK

PCH_AZ_SDIN0_R

2 33_0402_5%

13 14 22

1

2

1

RA9

HP/MIC1 JD(JD1) I2S_IN/I2S_OUT JD(JD2) TV Mode/LINE1-JD (JD3)

+VDDA_PVDD

2

1 2

1

Place RA9 close to codec

PCH_AZ_CODEC_RST#

<34>

Close to UA1 pin6

1

10

PCH_AZ_CODEC_SYNC

PCH_AZ_CODEC_SDIN0

<6>

5

DVDD

38 41 46

2 1

<6>

PCH_AZ_CODEC_SDOUT

VDD PVDD1 PVDD2

1

<6>

2

2

1 2

3

2 1

3

2 1

1

1

1

1 2

2

2

2 B

PCH_AZ_CODEC_SDOUT

6

DVDD_IO

27 40

CA48 10U_0603_6.3V6M

<6>

PCH_AZ_CODEC_BITCLK

AVDD1 AVDD2

CA47 0.1U_0402_25V6

PCH_AZ_CODEC_BITCLK

2

I2S I/F Float

CA46 10U_0603_6.3V6M

9

Close to UA1

Place closely to Pin 13.

1

EN_I2S_NB_CODEC#

+1.5V_RUN_AUDIO


CA45 0.1U_0402_25V6

UA1 <35>

3

<6>

1

CA18 4.7U_0603_6.3V6K

GND GND ACES_50279-0040N-001

2


CA17 0.1U_0402_25V6

@EMC@ DA7 L03ESDL5V0CC3-2_SOT23-3

@EMC@ CA24 1000P_0402_50V7K

@EMC@ CA19 1000P_0402_50V7K

@EMC@ CA23 1000P_0402_50V7K

@EMC@ CA22 1000P_0402_50V7K

@EMC@ DA6 L03ESDL5V0CC3-2_SOT23-3

5 6

LA5

BLM15PX600SN1D_2P

CA16 4.7U_0603_6.3V6K

1 2 3 4

CA9 10U_0603_6.3V6M

1 2 3 4

1

CA8 0.1U_0402_25V6

INT_SPKR_L+ INT_SPKR_LINT_SPKR_R+ INT_SPKR_R-

BLM15PX330SN1D_2P BLM15PX330SN1D_2P BLM15PX330SN1D_2P BLM15PX330SN1D_2P

CA50 0.1U_0402_25V6

2 2 2 2

CA11 0.1U_0402_25V6

EMC@ LA6 1 EMC@ LA7 1 EMC@ LA8 1 EMC@ LA9 1

CA10 4.7U_0603_6.3V6K

INT_SPK_L+ INT_SPK_LINT_SPK_R+ INT_SPK_R-

+3.3V_RUN_AUDIO CA11 close to pin9 CA10 close to pin3

@ RA39 0_0805_5%

+VDDA_AVDD1 CONN@ JSPK1

40 mils trace keep 20 mil spacing

+5V_RUN_AUDIO

@ RA4 0_0603_5%

Internal Speakers Header

+3.3V_RUN_AUDIO

1

+1.5V_RUN

@ RA3 0_0603_5%


1

+5V_RUN_AUDIO 1W x 1ch, 4ohm (Transducer spec is 8Ohm/0.5Watt per unit, there are two transducer units in one speaker box.)

2

2


Title

Codec _ALC3226 Size

Document Number

Date:


Rev 0.3

LA-A901P Sheet

21

of

53

2

1

+1.05V_RUN_VMM +3.3V_RUN_VDDA

J10 K8 K9 K10

1

1 2

2

1 2

2

CV97 0.01U_0402_16V7K

CV95 0.1U_0402_25V6

CV96 0.01U_0402_16V7K

CV94 10U_0603_6.3V6M

1

+3.3V_RUN_VDDIO

J2 C3 C4 C11 C12 K3 K4 K11 K12 J4

+3.3V_RUN_VDDA

NC VDDRXA1 VDDRX NC VDDTX0A1 VDDTX0A2 NC VDDTX1A1 VDDTX1A2 VGA_AVDD VGA_AVDD VGA_AVDD VGA_AVDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VDDSA VDDHRX_33 VDDHRX_33 VDDHTX0_33 VDDIO VDDIO VDDIO VDDIO VDDIO VDDXT3V

VSS VSS VSS VSS VGA_AVSS VGA_AVSS VGA_AVSS VGA_AVSS VGA_AVSS

1 2

1 2

1

1 2

2

1V Digital

VDDLP

C5 D5 D6 D7 D8 D9 D10 D11 E4 E11 F4 F5 F6 F7

<25> <25> <25> <25> <25> <25> <25> <25> <25> <25>

0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K

VMM2320_P0 VMM2320_N0 VMM2320_P1 VMM2320_N1 VMM2320_P2 VMM2320_N2 VMM2320_P3 VMM2320_N3 VMM2320_AUX VMM2320_AUX#

<25>

<9>

F8 F9 F10 F11 G4 G5

1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2

CV102 CV103 CV104 CV105 CV106 CV107 CV108 CV109 CV110 CV111

UV8A

VMM2320_P0_C VMM2320_N0_C VMM2320_P1_C VMM2320_N1_C VMM2320_P2_C VMM2320_N2_C VMM2320_P3_C VMM2320_N3_C VMM2320_AUX_C VMM2320_AUX#_C SRCDET

G1 G2 F1 F2 E1 E2 D1 D2 H1 H2 C2 J1

VMM2320_HPD

A13

PLTRST_VMM2320#

VMM_SPI_WP#

B5 B6 B1

VMM_SPI_CS# VMM_SPI_CLK VMM_SPI_DIN VMM_SPI_DO

A4 B3 B4 A3

+3.3V_RUN_VDDIO

1 VMM_GPIO9 @ RV73 1 SW_DPC_AUX RV74 SW_DPB_AUX 1 RV75 1 RED_2320 RV76 1 GREEN_2320 RV77 1 BLUE_2320 RV78 1 LP_CTL @ RV79

2 1M_0402_5%

2 1M_0402_5%

G6 G7 G8 G9 G10 G11 H4 D4

2 1M_0402_5%

2 150_0402_1%

2 150_0402_1%

2 150_0402_1%

2 100K_0402_5% J5 J11 J12 K5 H10 J6 J7 J8 J9

+3.3V_RUN_VMM

1 LP_CTL @ RV516

2 2.2K_0402_5%

2 CLK_27M_OUT_R 1 RV81

4

1

GND

2

1 2

CV115 22P_0402_50V8J

GND

2 1.8K_0402_5%

CV113 22P_0402_50V8J

2

K2 L2 M1 M2

RV80 1M_0402_5%

VMM3320BJGR_BGA168

YV2 27MHZ_12PF_X1E000021042600 1 3 IN OUT

D14 D13 C14 C13 B14 B13 C1 M12 M13 L3 B2 A5

VMM_GPIO4 VMM_GPIO5 VMM_GPIO6 VMM_GPIO7 VMM_GPIO8 VMM_GPIO9 LP_CTL LP_EN

1

H11 E12 D12

VDDLP

1 V Analog

1

1 2

2

1 2

1 2

CV93 0.01U_0402_16V7K

CV92 0.01U_0402_16V7K

CV91 0.1U_0402_25V6

+3.3V_RUN_VMM LV24 1 2 BLM15PX181SN1D_2P

E10 C7 C6

VDDTX0 VDDTX0 VDDTX1 VDDTX1

3.3V IO

1 2

1

1 2

2 1 2

1 2 1 2

1 2 1 2

J3 E5 H3 F3 D3

VDDRX VDDRX

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

H5 C10 H12 K6 K7

CV101 10U_0603_6.3V6M

CV89 0.01U_0402_16V7K

CV88 0.1U_0402_25V6

C8 C9 F12 G12

+1.05V_RUN

VDDRX_33 VDDTX0_33 VDDTX1_33 VGA_AVDD33 VGA_AVDD33

CV100 0.1U_0402_25V6

E3 G3

3.3V Analog

VDD VDD VDD VDD VDD VDD VDD VDD

CV99 0.01U_0402_16V7K

CV86 0.01U_0402_16V7K

CV85 0.01U_0402_16V7K

CV84 0.1U_0402_25V6

CV83 0.1U_0402_25V6

E6 E7 E8 E9 H6 H7 H8 H9

+1.05V_VMM_VDDTX CV90 10U_0603_6.3V6M

B

CV87 1U_0603_10V6K

LV23 1 2 BLM15PX181SN1D_2P

CV82 10U_0603_6.3V6M

+1.05V_RUN_VMM

+3.3V_RUN_VMM LV25 1 2 BLM15PX181SN1D_2P

UV8B

+1.05V_VMM_VDD

CV98 0.01U_0402_16V7K

LV22 1 2 BLM15PX181SN1D_2P

CLK_27M_IN

K1

CLK_27M_OUT

L1

RxP0 RxN0 RxP1 RxN1 RxP2 RxN2 RxP3 RxN3 RxAUXP RXAUXN RxSRCDET RxHPD

Tx0P0 Tx0N0 Tx0P1 Tx0N1 Tx0P2 Tx0N2 Tx0P3 Tx0N3 CAD0 Tx0AUXP Tx0AUXN Tx0DDCSCL Tx0DDCSDA Tx0HPD

RSTN_IN

Tx1P0 Tx1N0 Tx1P1 Tx1N1 Tx1P2 Tx1N2 Tx1P3 Tx1N3 CAD1 Tx1AUXP Tx1AUXN Tx1DDCSCL Tx1DDCSDA Tx1HPD

VDDIO VDDIO NC SPICS SPICLK SPIDI SPIDO GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 NC NC LP_CTL LP_EN

VGA_VSYNC VGA_HSYNC VGA_RP VGA_RN VGA_GP VGA_GN VGA_BP VGA_BN VGA_SCL VGA_SDA VGA_DET VGA_IREF NC

RX_STS TX0_STS TX1_STS TX2_STS

SSDA SSCL NC RxDDCSDA NC NC NC RxDDCSCL

XIN XOUT

B7 A7 B8 A8 B9 A9 B10 A10 A14 SW_DPC_AUX B11 SW_DPC_AUX# A11 B12 VMM_DPC_CTRLCLK A12 VMM_DPC_CTRLDAT A6 E13 E14 F13 F14 G13 G14 H13 H14 M14 J13 J14 K13 L14 K14

DPC_LANE_P0 <34> DPC_LANE_N0 <34> DPC_LANE_P1 <34> DPC_LANE_N1 <34> DPC_LANE_P2 <34> DPC_LANE_N2 <34> DPC_LANE_P3 <34> DPC_LANE_N3 <34> DPC_CA_DET <25,34> SW_DPC_AUX <25> SW_DPC_AUX# <25> VMM_DPC_CTRLCLK <25> VMM_DPC_CTRLDAT <25> DPC_DOCK_HPD <34> DPB_LANE_P0 <34> DPB_LANE_N0 <34> DPB_LANE_P1 <34> DPB_LANE_N1 <34> DPB_LANE_P2 <34> DPB_LANE_N2 <34> DPB_LANE_P3 <34> DPB_LANE_N3 <34> DPB_CA_DET <25,34> SW_DPB_AUX <25> SW_DPB_AUX# <25> VMM_DPB_CTRLCLK <25> VMM_DPB_CTRLDAT <25> DPB_DOCK_HPD <34>

SW_DPB_AUX SW_DPB_AUX# VMM_DPB_CTRLCLK VMM_DPB_CTRLDAT

L9 M9 M6 L6 M7 L7 M8 L8 L4 M4

B

VSYNC_2320 <26> HSYNC_2320 <26> RED_2320 <26> GREEN_2320 BLUE_2320

<26> <26>

CLK_DDC2_2320 DAT_DDC2_2320

M3 M5 L5

VMM2320_VGA_DET VMM2320_VGA_IREF VMM2320_VGA_NC

A1 A2

I2C1_SDA_VMM I2C1_SCL_VMM

<26> <26>

@ T108PAD~D

M11 M10 L12 L13 L11 L10

VMM3320BJGR_BGA168

+3.3V_RUN_VMM

1

RV210 100K_0402_5%

6 5 2 1

3

2 1

2

2

@

VMM_SPI_CS# VMM_SPI_DIN VMM_SPI_WP#

CV114

UV9

1 2 3 4

CS# VCC DO(IO1) HOLD#(IO3) WP#(IO2) CLK GND DI(IO0)

VMM_GPIO4 2 2.2K_0402_5% VMM_GPIO5 2 2.2K_0402_5%

1

2

RV82

2 RV83

2 RV84

1 @ RV517 @ RV518

1 @ RV519 RPV1

1 2 3 4

8 7 6 5

2.2K_0804_8P4R_5% RPV2 1 8 2 7 3 6 4 5

VMM_DPC_CTRLDAT VMM_DPC_CTRLCLK I2C1_SDA_VMM I2C1_SCL_VMM

0.1U_0402_25V6

8 7 6 5

2

VMM_DPB_CTRLCLK VMM_DPB_CTRLDAT VMM_GPIO8 VMM_GPIO7

+3.3V_RUN_VMM

1

1

3 5 4

1 6

QV21A DMN66D0LDW-7_SOT363-6

LP_EN A

EEPROM CV374 2200P_0402_50V7K

@

LP_EN#

@

4

1.05V_LP_EN QV21B DMN66D0LDW-7_SOT363-6

2

RV212 100K_0402_5% @

+1.05V_RUN_VMM

G

@

+3.3V_ALW2

@ QV20 SI3456DDV-T1-GE3_TSOP6 S

+1.05V_RUN +5V_ALW

D

Low Power Mode by external FET switch

SW_DPB_AUX# 1 1M_0402_5% VMM_GPIO6 1 2.2K_0402_5% 1 SRCDET 1M_0402_5% VMM_SPI_WP# 2 2.2K_0402_5%

VMM_SPI_HOLD VMM_SPI_CLK VMM_SPI_DO

2.2K_0804_8P4R_5% SW_DPC_AUX# 1 2 1M_0402_5% RV85 VMM_SPI_CS# 2 1 10K_0402_5% RV86 VMM_SPI_HOLD 2 1 2.2K_0402_5% RV87 VMM2320_VGA_DET 2 1 10K_0402_5% RV88

W25X10CVSNIG_SO8

VMM2320_VGA_IREF 1 3.74K_0402_1%

A

2 RV89

VMM2320 Operation power consumption for 1.0V=1.464A (Max) +1.05V_RUN

+1.05V_RUN_VMM PJP24

1

2

PAD-OPEN1x1m +3.3V_RUN

+3.3V_RUN_VMM PJP25

1

2

PAD-OPEN1x1m


1

Title

DP 1.2 MST HUB Size

Document Number

Date:


Rev 0.3

LA-A901P Sheet

22

of

53

5

4

3

2

1

+5V_TSP TOUCH__INTR#: Close lid >> TP_EN = 0 >> Disable touch events Open lid >> TP_EN = 1 >> Enable touch events

JEDP1

4

<10,12> 2

CAM_MIC_CBL_DET# Pin15: LOOP_BACK +BL_PWR_SRC

1

3

<21>

1

1 2

1

USBP5_DUSBP5_D+

2

<21>

DMIC_CLK0

EDP_U_HPD LCD_TST

1 1 1 1 1 1

0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K

EDP_U_AUX# <10> EDP_U_AUX <10> EDP_U_LANE_P0 <10> EDP_U_LANE_N0 <10> EDP_U_LANE_P1 <10> EDP_U_LANE_N1 <10>

For Touchscreen

DISP_ON

2

2

RV2 4.7K_0402_5%

BAT54CW_SOT323-3

_BKEN_EC

D

S

2 G

3.3V_TS_EN

<10>

1

<36> 1

BIA_PWM_EC

_BKLEN

1

BIA_PWM_EC

<6,12>

3

<10>

3

2

EDP_BIA_PWM

S

D

3

QV7 L2N7002WT1G_SC-70-3

EDP_BIA_PWM

1

Close to JEDP1.1

DV2 3

+5V_RUN QV8 LP2301ALT1G_SOT23-3

2 G

1 2

@

1 2

1 2

1 2

@

1 2

@

Close to JEDP1.40

+5V_TSP

RV6 47K_0402_5%

Close to JEDP1.33

C

+5V_RUN

+3.3V_RUN CA7 0.1U_0402_25V6

Close to JEDP1.11,12

+5V_TSP

@

+3.3V_CAM

CZ2 0.1U_0402_16V4Z

1

<11>

<7,12>

CZ1 0.1U_0402_25V6

@

<11>

USBP4+

<10>

CV1 2 CV2 2 CV3 2 CV4 2 CV5 2 CV6 2

LCD_CBL_DET#

CV8 0.1U_0402_25V6

2

USBP4-

+LCDVDD EDP_U_AUX#_C EDP_U_AUX_C EDP_U_LANE_P0_C EDP_U_LANE_N0_C EDP_U_LANE_P1_C EDP_U_LANE_N1_C

+LCDVDD

CV7 0.1U_0603_50V7K

1

3

<35>

1

RV1 4.7K_0402_5%

2

3

ESD depop location

DV1

BIA_PWM

4

2

BIA_PWM 2 BLM15BB221SN1D_2P

EMC@ LV1 1 DISP_ON

C

Close to JEDP1.24~27

2

D

ACES_50398-04041-001 CONN@

+BL_PWR_SRC

LV27

1

DLW21HN900HQ2L_4P

@EMC@ DV4 AZC199-02SPR7G_SOT23-3

DMIC0 +3.3V_RUN +3.3V_CAM

3

<12>

2

TOUCH__INTR#

@EMC@ CA6 100P_0402_50V8J

G1 G2 G3 G4 G5

EMC@ 1 USBP4_DUSBP4_D+

@EMC@ CA5 100P_0402_50V8J

D

41 42 43 44 45

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

<35>

BAT54CW_SOT323-3

B

B

Backlight POWER

WebCAM

+BL_PWR_SRC

+LCDVDD

2

<10,36>

3

ENVDD_PCH

USBP5+

<11>

USBP5-

4

1

2

4

3

3

USBP5_D-

EN_LCDPWR

BAT54CW_SOT323-3 1

AP2821KTR-G1_SOT23-5

@

4

EN

3

S

2 1 47K_0402_5%

3

5

2 G

<11>

USBP5_D+

D

1 RV5 2

VIN 1

QV2 L2N7002WT1G_SC-70-3

LZ1 EMC@

GND

2

LCD_VCC_TEST_EN

2

1 2

2

3

1

S

<35>

2

PAD-OPEN1x1m

RV3 100K_0402_5%

2 G

D

AO6405_TSOP6

PWR_SRC_ON

change back to CCD_OFF at Goliad project

VOUT VIN

DV3 CV12 0.1U_0603_50V7K

3.3V_CAM_EN#

1

1

10U_0603_6.3V6M

G

1

S

RV4 270K_0402_5%

3

CV11 1000P_0402_50V7K

1

UV24 2

CV10 0.01U_0402_16V7K

6 5 2 1

4 QZ1 LP2301ALT1G_SOT23-3

A

+EDP_VDD PJP29 1

1

+3.3V_RUN

@ CV9 2 1

2

QV1 D

+3.3V_CAM

<12>

LCDVDD POWER

+3.3V_ALW +PWR_SRC

<36>

A

EN_INVPWR

DLW21HN900HQ2L_4P


4

3

2

Title

eDP CONN & Touch screen Size

Document Number

Date:


Rev 0.3

LA-A901P Sheet 1

23

of

53

5

4

3

2

1

LV3 EMC@ <10> <10>

DDI1_LANE_N3

2

TMDS_CLK#_C 1 0.1U_0402_10V7K

1

2

TMDS_CLK_C 1 0.1U_0402_10V7K

4

CV13

DDI1_LANE_P3

CV14

1

2

4

3

2

TMDS_CON_CLK#

3

TMDS_CON_CLK

DLW21HN900HQ2L_4P

D

D

ESD Request LV6 EMC@ <10> <10>

DDI1_LANE_P2

2

TMDS_P0_C 1 0.1U_0402_10V7K

1

2

TMDS_N0_C 1 0.1U_0402_10V7K

4

CV17

DDI1_LANE_N2

CV18

1

2

4

3

2

TMDS_CON_P0

3

TMDS_CON_N0

+3.3V_RUN

2

1

2

@EMC@ CV378 22U_0603_6.3V6M

1

@EMC@ CV377 22U_0603_6.3V6M

DLW21HN900HQ2L_4P

+5V_RUN

TMDS_CON_N1

3

TMDS_CON_P1

<10>

DDI1_LANE_P1

CV22

4

3

2 CV28

TMDS_P2_C 1 0.1U_0402_10V7K

2 CV29

TMDS_N2_C 1 0.1U_0402_10V7K

LV12 1 1

OUT 3

2 DDI1_LANE_P0

CV27 10U_0603_6.3V6M

<10>

C @ CV26 0.1U_0402_10V7K

GND

DLW21HN900HQ2L_4P

UV2 AP2330W-7_SC59-3

C

Close to JHDMI1 (Place on TOP) +VHDMI_VCC

1

2

2

2

@

1

1

4

2

1

TMDS_P1_C 1 0.1U_0402_10V7K

1

TMDS_N1_C 1 0.1U_0402_10V7K

2

IN

2 CV21

1

DDI1_LANE_N1

2

<10>

CV23 0.1U_0402_16V4Z

LV9 EMC@

EMC@

2

TMDS_CON_P2

2

JHDMI1 CONN@ HDMI_HPD_SINK

<10>

DDI1_LANE_N0

4

19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

TMDS_CON_N2

3 4 3 DLW21HN900HQ2L_4P

U_DPB_CTRLDAT_R U_DPB_CTRLCLK_R HDMI_CEC TMDS_CON_CLK# TMDS_CON_CLK TMDS_CON_N0 TMDS_CON_P0 TMDS_CON_N1 TMDS_CON_P1 TMDS_CON_N2 TMDS_CON_P2

+3.3V_RUN

B

HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CKGND CK_shield GND CK+ GND D0GND D0_shield D0+ D1D1_shield D1+ D2D2_shield D2+

20 21 22 23

B

2

CONCR_099BKAC19YBLCNF

U_DPB_CTRLCLK

6

<10>

U_DPB_CTRLDAT

4

+VHDMI_VCC

U_DPB_CTRLCLK_R

1 RV7

5

<10>

QV3A DMN66D0LDW-7_SOT363-6

1

+3.3V_RUN

2 2.2K_0402_5% HDMI_CEC 2 10K_0402_5%

U_DPB_CTRLDAT_R

3

1 RV9

1 @ RV8

2 2.2K_0402_5%

QV3B DMN66D0LDW-7_SOT363-6

RV19

2 2 2 2 2 2 2 2

1

470_0402_1% 470_0402_1% 470_0402_1% 470_0402_1% 470_0402_1% 470_0402_1% 470_0402_1% 470_0402_1%

2 10K_0402_5%

3

1

HDMI_HPD_SINK

D

A

DPB_HPD

S

<10>

1 RV20

2 20K_0402_5%

HDMI_OB

1 G

2

1 1 1 1 1 1 1 1

1

2

RV18 1M_0402_5%

+3.3V_RUN

RV10 RV11 RV12 RV13 RV14 RV15 RV16 RV17

D

3

TMDS_P2_C TMDS_N2_C TMDS_P1_C TMDS_N1_C TMDS_P0_C TMDS_N0_C TMDS_CLK_C TMDS_CLK#_C

+3.3V_RUN

S

2 G

QV4 L2N7002WT1G_SC-70-3

QV5 L2N7002WT1G_SC-70-3

A DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

Title

HDMI CONN Size

Document Number

Date:


LA-A901P Sheet

Rev 0.3 24

of

53

3

1 RV69 1

D

RV71

H12 UMA PS8338+PS8339

RV67

H12 Entry

1

PS8339

RV68 1 RV70

H14 DSC

1

PS8338

H14 UMA

RV72

DDI2_LANE_P0 DDI2_LANE_N0

<10> <10>


<10> <10>


1 2

1 2

1 2

1

1 CV71 1 CV72 1 CV73 1 CV74 1 CV75 1 CV76 1 CV77 1 CV78

<10> DDI2_LANE_P3 <10> DDI2_LANE_N3

PS8338

2

1 2

2 OUT1_CA_DET 1M_0402_5% 2 OUT2_CA_DET 1M_0402_5% 2 VMM2320_AUX 100K_0402_5% 2 WIGIG_AUX 100K_0402_5%

1

<10> <10>

DDI2_LANE_P0_C 2 2 0.1U_0402_25V6DDI2_LANE_N0_C 0.1U_0402_25V6 DDI2_LANE_P1_C 2 2 0.1U_0402_25V6DDI2_LANE_N1_C 0.1U_0402_25V6 DDI2_LANE_P2_C 2 2 0.1U_0402_25V6DDI2_LANE_N2_C 0.1U_0402_25V6 DDI2_LANE_P3_C 2 2 0.1U_0402_25V6DDI2_LANE_N3_C 0.1U_0402_25V6

+3.3V_RUN

H15 UMA H15D_En

PS8338B_P1

PS8338B_PC11 PS8338B_PC20

PS8338 RV100 4.7K_0402_5% 2 1

@ RV65 4.7K_0402_5% 2 1

@ RV63 4.7K_0402_5% 2 1

@ RV64 4.7K_0402_5% 2 1

@ RV62 4.7K_0402_5% 2 1

12 13 15 16

4 3 2 1 60

11 19 52 61

PS8338B_PEQ

+3.3V_RUN_VMM 1

OUT1_D0p OUT1_D0n OUT1_D1p OUT1_D1n

IN_D0p IN_D0n

OUT1_D2p OUT1_D2n

IN_D1p IN_D1n

OUT1_D3p OUT1_D3n

IN_D2p IN_D2n

OUT2_D0p OUT2_D0n

IN_D3p IN_D3n

OUT2_D1p OUT2_D1n OUT2_D2p OUT2_D2n

IN_CA_DET IN_HPD I2C_CTL_EN Pl1/SCL_CTL Pl0/SDA_CTL

OUT2_D3p OUT2_D3n OUT1_AUXp_SCL OUT1_AUXn_SDA

IN_DDC_SCL IN_DDC_SDA IN_AUXp IN_AUXn

OUT2_AUXp_SCL OUT2_AUXn_SDA

CFG0 CFG1 PC10 PC11 PC20 PC21

OUT1_CA_DET OUT1_HPD OUT2_CA_DET OUT2_HPD SW PEQ PD CEXT REXT

GND GND GND PAD(GND)

50 49

VMM2320_P0 <22> VMM2320_N0 <22>

47 46

VMM2320_P1 <22> VMM2320_N1 <22>

45 44 42 41

VMM2320_P3 <22> VMM2320_N3 <22>

40 39 37 36 35 34 32 31 26 27

<34>

DPB_DOCK_AUX

1 2

2 1 SW_DPB_AUX_C CV119 0.1U_0402_10V7K DPB_DOCK_AUX

3

B

<22> <34>

SW_DPB_AUX#

DPB_DOCK_AUX#

4 5

2 1 SW_DPB_AUX#_C CV120 0.1U_0402_10V7K DPB_DOCK_AUX#

6 7

VCC BE3

B0

A3

BE1 A1

B3 BE2

B1

A2

GND

B2

14 13 12

<22> VMM_DPB_CTRLCLK

<22>

<34>

11 10 9

<34>

2 CV122

DPC_DOCK_AUX

<22> VMM_DPB_CTRLDAT <22>

SW_DPC_AUX

SW_DPC_AUX#

DPC_DOCK_AUX#

2 CV123

1 2

SW_DPC_AUX_C 1 0.1U_0402_10V7K DPC_DOCK_AUX

3 4 5

SW_DPC_AUX#_C 1 0.1U_0402_10V7K DPC_DOCK_AUX#

6

8

7

PI3C3125LEX_TSSOP14

WIGIG_LANE_P3 WIGIG_LANE_N3

<30> <30>

OUT1_CA_DET

33 38

OUT2_CA_DET

18 8 14 17 20

PS8338_SW PS8338B_PEQ

VMM2320_HPD WIGIG_HPD

<30> <30> <22>

<30>

C

+3.3V_RUN_VMM 1

CV121 2

BE0 A0

VCC BE3

B0

A3

BE1 A1

B3 BE2

B1

A2

GND

B2

14 13 12

VMM_DPC_CTRLCLK

<22> B

11 10 9

VMM_DPC_CTRLDAT

<22>

8

PI3C3125LEX_TSSOP14

D

S

1 2

RV91 100K_0402_5%

RV90 100K_0402_5%

1

+3.3V_RUN_VMM

3

+3.3V_RUN_VMM 1

<30> <30>

UV12

BE0 A0

2

<30> <30>


0.1U_0402_25V6

UV11 SW_DPB_AUX

<30> <30>


WIGIG_AUX WIGIG_AUX#

43 48

0.1U_0402_25V6

<22>


VMM2320_AUX <22> VMM2320_AUX# <22>

28 29

AUX/DDC SW for DPC to E-DOCK

CV118 2

D

VMM2320_P2 <22> VMM2320_N2 <22>

PS8338BQFN60GTR-A0_QFN60_5X9

Port switching control or priority configuration. Internal pull down ~150KΩ, 3.3V I/O For Control Switching Mode (CFG0 = L): SW = L: Port1 is selected (default) SW = H: Port2 is selected For Automatic Switching Mode (CFG0 = H): SW = L: Port1 has higher priority when both ports are plugged (default) SW = H: Port2 has higher priority when both ports are plugged

@

AUX/DDC SW for DPB to E-DOCK

9 10

22 23 U_DPC_AUX_C 24 2 2 0.1U_0402_25V6 U_DPC_AUX#_C 25 0.1U_0402_25V6 PS8338_CFG0 59 58 PS8338B_PC10 56 PS8338B_PC11 55 PS8338B_PC20 54 PS8338B_PC21 53

PS8338B_PC21

PS8338

6 7

VDD33 VDD33 VDD33 VDD33 VDD33

CV60 2.2U_0402_6.3V6M

H15U_En

1 CV79 1 CV80

<10> U_DPC_AUX <10> U_DPC_AUX#

@

PS8338

UV7 5 21 30 51 57

for TMDS signal need SCL/SDA to P22,23

PS8338B_PC10

@ RV61 4.7K_0402_5% 2 1

C

RV53 4.7K_0402_5% 2 1

PS8338

@ RV58 4.7K_0402_5% 2 1

H15 DSC

DPC_HPD PS8338B_P1 PS8338B_P0

@ RV57 4.7K_0402_5% 2 1

PS8338

@ RV56 4.7K_0402_5% 2 1

H14U_En

<10>

@ RV55 4.7K_0402_5% 2 1

PS8338 @ RV54 4.7K_0402_5% 2 1

H14D_En

Dock has high priority when both ports plugged

1

@

RV60

CV70 0.1U_0402_25V6

DP SWITCH

CV69 0.1U_0402_25V6

PCB

CV66 0.1U_0402_25V6

1

CV62 0.01U_0402_16V7K

1 RV52

CV61 0.01U_0402_16V7K

2 PS8338_CFG0 4.7K_0402_5% 2 PS8338_SW 4.7K_0402_5% 2 PS8338B_P0 4.7K_0402_5% 2 VMM2320_AUX# 100K_0402_5% 2 WIGIG_AUX# 100K_0402_5%

1 RV51

1

+3.3V_RUN

CV62 CV90 close to pin30 &57 CV66,CV69,CV70 close to pin5,21,51

+3.3V_RUN

@

2

2

4

RV50 4.99K_0402_1% 2 1

5

DPB_CA_DET#

DPB_CA_DET

DPB_CA_DET

1 <22,34>

3

DPC_CA_DET# D

S

2 G

QV9 L2N7002WT1G_SC-70-3

<22,34>

DPC_CA_DET

DPC_CA_DET

2 G

QV10 L2N7002WT1G_SC-70-3

A

A

1 RV508

DPB_CA_DET 2 1M_0402_5%

1 RV509

DPC_CA_DET 2 1M_0402_5%

DP

HDMI

DPB_CA_DET

0

1

DPC_CA_DET

0

1


Title

DP SW Size

4

3

2

Rev 0.3

LA-A901P Date:

5


Sheet 1

25

of

53

5

4

3

2

1

+3.3V_RUN

1 RV250 1 RV251

VGA SW for MB/DOCK

2 DAT_DDC2_2320 2.2K_0402_5% 2 CLK_DDC2_2320 2.2K_0402_5%

+5V_RUN

VGA SW D

source from VMM2320

PCB

VGA SWITCH

H12 UMA

NA

H12 Entry

+3.3V_RUN

PI3V713

H15 UMA

PI3V713

H15D_En

NA

H15U_En

NA

TEST

8

Reserved

3 11 28 31 33

R2 G2 B2 H2_OUT V2_OUT SDA2 SCL2

GND GND GND GND GPAD

26 24 21 19 17 13 15

RED_DOCK <34> GREEN_DOCK <34> BLUE_DOCK <34> HSYNC_DOCK <34> VSYNC_DOCK <34> DAT_DDC2_DOCK <34> CLK_DDC2_DOCK <34>

ESD Request

PI3V713-AZLEX_TQFN32_6X3

+3.3V_RUN +3.3V_RUN

SEL1/SEL2

Chanel

Source

0

A=B1

MB

1

A=B2

APR/SPR

1

2

1

2

1

2

1

2

1

2

+5V_RUN

1

2

1

2

1

2

@EMC@ CV380 22U_0603_6.3V6M

H15 DSC

2 4.7K_0402_5%

@EMC@ CV379 22U_0603_6.3V6M

NA

1

CV144 0.1U_0402_16V4Z

H14U_En

RV121

RED_CRT GREEN_CRT BLUE_CRT HSYNC_CRT VSYNC_CRT DAT_DDC2_CRT CLK_DDC2_CRT

27 25 22 20 18 12 14

CV124 0.1U_0402_16V4Z

NA

+3.3V_RUN

SEL

29

R1 G1 B1 H1_OUT V1_OUT SDA1 SCL1

D

4 23 32

CV125 0.1U_0402_16V4Z

H14D_En

30

VDD VDD VDD

CV126 0.1U_0402_16V4Z

PI3V713

DOCKED

5V VDD

CV127 @ 0.01U_0402_16V7K

H14 UMA

DOCKED

DAT_DDC2_2320 CLK_DDC2_2321

R G B H_SOURCE V_HOURCE SDA_SOURCE SCL_SOURCE

16

CV128 @ 0.01U_0402_16V7K

C

PI3V713

<22> RED_2320 <22> GREEN_2320 <22> BLUE_2320 <22> HSYNC_2320 <22> VSYNC_2320 <22> DAT_DDC2_2320 <22> CLK_DDC2_2320 <28,31,35>

NA

H14 DSC

+3.3V_RUN

UV16 1 2 5 6 7 9 10

C

Close to JCRT1 (Place on TOP)

2

1 IN

3

2 1

@

2

@

1

2

40mils

1

3.3P_0402_50V8C CV56

2

BLM15BB470SN1D_2P 3.3P_0402_50V8C CV55

CV53

1

2.2P_0402_50V8C

CV52

2

2.2P_0402_50V8C

CV51

2.2P_0402_50V8C

RV34 150_0402_1% 2 1

RV33 150_0402_1% 2 1

RV32 150_0402_1% 2 1

2

1

B

+CRT_VCC

BLM15BB470SN1D_2P

EMC@ LV18 1

2

BLM15BB470SN1D_2P

OUT

2 3.3P_0402_50V8C CV54

BLUE_CRT

3

2

1

EMC@ LV17

UV4 AP2330W-7_SC59-3

GND

2

1

1

3 1

1 EMC@ LV16

GREEN_CRT

@EMC@ DV6 PJDLC05C_SOT23-3

RED_CRT B

@EMC@ DV5 PJDLC05C_SOT23-3

2

+5V_RUN

@

1

2 @

CV50 1U_0402_6.3V6K JCRT1 CONN@

T87 PAD~D

6 11 1 7 12 2 8 13 3 9 14 4 10 15 5

JCRT-11 RED GREEN

+CRT_VCC

RV38 1K_0402_5% 1 2

RV37 1K_0402_5% 1 2

VSYNC_CONN M_ID2#

1

CLK_DDC2_CRT 2

1

2

EMC@ LV19 EMC@ LV20

BLM15AG121SN1D_L0402_2P 1

2

4

3

16 17

G G

C-H_13-122015XX-A

A

1


2

Compal Electronics, Inc.


2

BLM15AG121SN1D_L0402_2P EMC@ CV58 12P_0402_50V8J

VSYNC_CRT A

1

EMC@ CV59 12P_0402_50V8J

HSYNC_CRT

CV57 0.1U_0402_16V4Z

RV36 2.2K_0402_5% 2 1

@

DAT_DDC2_CRT

@

RV35 2.2K_0402_5% 2 1

HSYNC_CONN BLUE

2

Title

VGA SW & VGA Conn Size

Document Number

Date:


Rev 0.3

LA-A901P Sheet 1

26

of

53

5

4

3

2

1

D

D

+3.3V_M

+3.3V_M_TPM PJP11 1

2

PAD-OPEN1x1m

RZ10

JUSH1

<11> <11>

22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

USBP6USBP6+

<36> USH_SMBCLK <36> USH_SMBDAT <35> BCM5882_ALERT#

AT97SC3205_TSSOP28~D

+3.3V_RUN

+3.3V_SUS +3.3V_SUS +3.3V_RUN +5V_RUN <9> PLTRST_USH# <35> USH_PWR_STATE# <10,12> LESS_DET#

@

+5V_RUN

5 13 14 15 27 28

@

NBO_1 NBO_2 NBO_3 NBO_4 NBO_5 NBO_6

GND GND GND GND

USH CONN

9 8

1

TESTBI TESTI

2

MISO MOSI SPI_CLK SPI_CS# SPI_RST# PIRQ#

C

USH_PWR_STATE# 2 1M_0402_5%

1

@

25 18 11 4

1 2 17 6 7

1

26 23 21 22 16 20

V_BAT GPIO_1 GPIO_2 GPIO_3 GPIO-Express-00 PP/GPIO

2

SPI_DINTPM SPI_DOTPM SPI_CLKTPM PCH_SPI_CS2#_R

VCC VCC VCC VCC

1

1

1 2

1 RZ9

2

2 1 1

RZ8 12

CZ12 0.1U_0402_25V6

2

PCH_PLTRST#_EC <12> TPM_PIRQ#

USH_SMBCLK 2 2.2K_0402_5% USH_SMBDAT 2 2.2K_0402_5%

1 3 10 19 24

CZ11 0.1U_0402_25V6

@EMC@ @EMC@ CZ9 RZ35 0.1U_0402_25V6 33_0402_5%

B

33_0402_5% 33_0402_5% 33_0402_5% 0_0402_5%

+3.3V_SUS

UZ1

CZ10 0.1U_0402_25V6

SPI_CLKTPM

2

1 2

2

<9,30,35,36>

2 2 2 2

CZ7 2200P_0402_50V7K

1 1 1 1

CZ6 2200P_0402_50V7K

RZ30 RZ29 RZ26 @ RZ17

<7> PCH_SPI_DIN <7> PCH_SPI_DO <7> PCH_SPI_CLK <7> PCH_SPI_CS2#

CZ5 4700P_0402_25V7K

C

@ CZ4 0.1U_0402_25V6

1

+3.3V_M_TPM

<7,12>

USH_DET#

CONN@

GND2 GND1 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 E-T_6705K-Y20N-00L

Close to JUSH1

B

2

@EMC@ CZ68 0.047U_0402_16V4Z

1

PLTRST_USH#

For ESD solution

A

A


4

3

2

Title

USH & TPM Size

Document Number

Date:


Rev 0.3

LA-A901P Sheet 1

27

of

53

28 31

LAN_WAKE#

2 3

LAN_DISABLE#_R

SMB_CLK SMB_DATA LANWAKE_N LAN_DISABLE_N

VDD3P3_4 26 27 25

TP_LAN_JTAG_TDI TP_LAN_JTAG_TDO TP_LAN_JTAG_TMS TP_LAN_JTAG_TCK

32 34 33 35

LED0 LED1 LED2

2

LOM_ACTLED_YEL# LOM_SPD100LED_ORG# LOM_SPD10LED_GRN#

1

1 2

2

2

2

1

1

GND

VDD0P9_11 VDD0P9_40 VDD0P9_22 VDD0P9_16 VDD0P9_8

6 1

VCT_LAN_R1

2

@ RL3 +RSVD_VCC3P3_1 RL6

LAN_TX0+L

0_0402_5% 1 4.7K_0402_5%

2

+3.3V_LAN

CTRL0P9 VSS_EPAD

2

LAN_TX0-L

+3.3V_LAN_OUT

2

1

@ RL8

15 19 29 +0.9V_LAN 47 46 37

0_0603_5%

+3.3V_LAN

3

LAN_TX1+L

6

LAN_TX1-L

7

LAN_TX2+L

9

LAN_TX2-L

10

LAN_TX3+L

11

LAN_TX3-L

12

43 11 40 22 16 8

<26,31,35>

7

+0.9V_LAN

49

REGCTL_PNP10 1 2 4.7UH_BRC2012T4R7MD_20% LL1 Idc_min=500mA DCR=100mohm

WGI218LM-QQ89-B0_QFN48_6X6~D

13

DOCKED LOM_ACTLED_YEL# LOM_SPD100LED_ORG# LOM_SPD10LED_GRN#

15 16 42 5 43

1: TO DOCK 0: TO RJ45

UL4

5 4

DOCKED

1

TEST_EN RBIAS

1

LAN_TX3+L LAN_TX3-L

2

2 2.2_0603_5% 2 2.2_0603_5%

CL4 10U_0603_6.3V6M

IN

GND

12

RL13 3.01K_0402_1%

OUT

25MHZ_18PF_7V25000034

RL12 1K_0402_5%

4

RES_BIAS

CL14 27P_0402_50V8J

CL13 27P_0402_50V8J

Note: +1.0V_LAN will work at 0.95V to 1.15V

1

30

XTAL_OUT XTAL_IN

VDD0P9_43

LAN_TX3+ EMC@ RL27 1 LAN_TX3- EMC@ RL28 1

2

1

LAN_TEST_EN

2

YL1 3

9 10

XTALO XTALI

JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TCK

VDD3P3_15 VDD3P3_19 VDD3P3_29 VDD0P9_47 VDD0P9_46 VDD0P9_37

JTAG

PAD~D PAD~D

RL11 1M_0402_5%

2

1 2

1 2

1 2

1 2

1 2

2 0_0402_5%

VDD3P3_IN

23 24

CL3 0.1U_0402_10V7K

CL8 0.1U_0402_10V7K

CL11 0.1U_0402_10V7K

CL10 0.1U_0402_10V7K

CL9 0.1U_0402_10V7K

CL12 22U_0603_6.3V6M

XTALO_R 1 @ RL10

RSVD_VCC3P3_1

LAN_DISABLE#_R

@ T88 @ T89

+0.9V_LAN

SVR_EN_N

1

MDI_PLUS3 MDI_MINUS3

LAN_TX2+L LAN_TX2-L

CL7 1U_0603_10V6K

<35>

@ RL9 10K_0402_5%

1

SMBus Device Address 0xC8


LAN_TX1+L LAN_TX1-L

2 2.2_0603_5% 2 2.2_0603_5%

1

<12,36>

PERp PERn

2 2.2_0603_5% 2 2.2_0603_5%


VDD VDD VDD VDD VDD VDD VDD

1 CL6

<7> SML0_SMBCLK <7> SML0_SMBDATA

PETp PETn


20 21

2

CL5

41 42

17 18

1

1

LAN_TX0+L LAN_TX0-L

2

PCIE_PTX_GLANRX_N3

2 CL2


LAN ANALOG SWITCH

+3.3V_LAN

2 2.2_0603_5% 2 2.2_0603_5%

1

1 2 0_0402_5%

@ RL7

<11>

2

1

PM_LANPHY_ENABLE

@ RL5 10K_0402_5%

D

PCIE_PTX_GLANRX_P3

PE_CLKP PE_CLKN

MDI

PCIE_PRX_GLANTX_N3

<11>

38 39

PCIE

<11> +3.3V_LAN

44 45 1 PCIE_PRX_GLANTX_P3_C 0.1U_0402_10V7K 1 PCIE_PRX_GLANTX_N3_C 0.1U_0402_10V7K 2 PCIE_PTX_GLANRX_P3_C 0.1U_0402_10V7K 2 PCIE_PTX_GLANRX_N3_C 0.1U_0402_10V7K

2 CL1

SMBUS

<7> CLK_PCIE_LAN <7> CLK_PCIE_LAN# PCIE_PRX_GLANTX_P3



CL27 0.1U_0402_25V6

<11>

CLK_REQ_N PE_RST_N

13 14

CL26 0.1U_0402_25V6

2 @ RL4

<7,12> LANCLK_REQ# <9> PLTRST_LAN#

48 36

CL25 0.1U_0402_25V6

1 @ RL2

LANCLK_REQ#

LED

2

@ RL1

<12>

Layout Notice : Place bead as close UL4 as possible

UL1 TP_LAN_JTAG_TMS 10K_0402_5% TP_LAN_JTAG_TCK 2 10K_0402_5% LANCLK_REQ# 1 4.7K_0402_5%

1

1

1

+3.3V_LAN

2

39 30 21 14 8 4 1

3

2

4

2

5

B0+ B0-

A0+ A0-

B1+ B1-

A1+

B2+ B2-

A1-

B3+ B3-

A2+ A2-

LEDB0 LEDB1 LEDB2

A3+

C0+ C0-

A3-

C1+ C1-

SEL

C2+ C2-

LEDA0 LEDA1 LEDA2

C3+ C3LEDC0 LEDC1 LEDC2

PD

38 37

SW_LAN_TX0+ SW_LAN_TX0-

34 33

SW_LAN_TX1+ SW_LAN_TX1-

29 28

SW_LAN_TX2+ SW_LAN_TX2SW_LAN_TX3+ SW_LAN_TX3-

25 24 17 18 41

D

SW_ACTLED_YEL# SW_100_ORG# SW_10_GRN#

36 35 32 31 27 26 23 22 19 20 40

DOCK_LOM_TRD0+ DOCK_LOM_TRD0-

<34> <34>


<34> <34>


<34> <34>


<34> <34>

DOCK_LOM_ACTLED_YEL# <34> DOCK_LOM_SPD100LED_ORG# <34> DOCK_LOM_SPD10LED_GRN# <34>

PAD_GND

PI3L720ZHEX_TQFN42_9X3P5

C

C

Place CL3, CL4 and LL1 close to UL1 2

3.3V_WWAN_EN 100K_0402_5%

+3.3V_WWAN 1

1 RZ40

PJP32 PAD-OPEN1x1m

VOUT2 VOUT2 GPAD

10 9 8

1 2 CZ23 470P_0402_50V7K +3.3V_LAN_UZ2 1

15

2

APE8990GN3B_SON14_2X3

2

+3.3V_LAN

1

1 PJP13

2

CT2

VIN2 VIN2

1 2 CZ49 470P_0402_50V7K

11

1

ON2

12

2 0.1U_0402_10V7K CL19 0.1U_0402_10V7K

6 7

GND

+3.3V_WWAN_UZ2 1 @ CZ24

CL18 470P_0402_50V7K

CT1

VBIAS

5

SIO_SLP_LAN#

VOUT1 VOUT1

ON1

4

+5V_ALW <9,36>

VIN1 VIN1

3

3.3V_WWAN_EN

14 13

2

UZ2 1 2 <35>

+3.3V_LAN

2

+3.3V_ALW

RJ45 LOM circuit +3.3V_LAN:20mils

TL1 PAD-OPEN1x2m @CZ50 0.1U_0402_10V7K

SW_LAN_TX1- 1

1:1

TD1+

TX1+

JLOM1

24 NB_LAN_TX1LAN_ACTLED_YEL# 1 RL14

2

LAN_ACTLED_YEL_R# 150_0402_5%

10 9

SW_LAN_TX1+ 2

TD1TX1-

23 NB_LAN_TX1+

+3.3V_LAN B

3

WLAN_LAN_DISBL#

UL2 TC7SH08FU_SSOP5~D

<35>

TDCT2 TD2+

TXCT1 TXCT2 TX2+

1:1

22

Z2805

21 Z2807 20 NB_LAN_TX0-

1

1

4 SW_LAN_TX0- 5

2

4

2

P

0.1U_0402_10V7K

O A

G

2

B

3

LOM_SPD10LED_GRN#

1

CL17 0.47U_0603_10V7K

LOM_SPD100LED_ORG#

CL16 0.47U_0603_10V7K

5

@ CL15 1 2

TDCT1

SW_LAN_TX0+ 6

TD2-

TX2-

19 NB_LAN_TX0+

NB_LAN_TX3-

8

NB_LAN_TX3+

7

NB_LAN_TX1-

6

NB_LAN_TX2-

5

NB_LAN_TX2+

4

NB_LAN_TX1+

3

NB_LAN_TX0-

2

NB_LAN_TX0+

1

LED_10_GRN# SW_LAN_TX3- 7 QL1A DMN66D0LDW-7_SOT363-6 SW_ACTLED_YEL# LAN_ACTLED_YEL# 1 6

1:1

TD3+

TX3+

1 RL19 LED_100_ORG# 1 RL20

18 NB_LAN_TX3-

LED_10_GRN_R# 150_0402_5% LED_100_ORG_R# 2 150_0402_5% 2

11 13 12

SW_LAN_TX3+ 8

TD3-

17 NB_LAN_TX3+

Yellow LED+ PR4PR4+

B

PR2PR3PR3+ GND PR2+ GND PR1GND PR1+ GND

17 16 15 14

Green LEDOrange LEDGreen-Orange LED+ SANTA_130456-511

2

TX3-

CONN@

Yellow LED-

Z2806

15 Z2808 14 NB_LAN_TX2-

SW_LAN_TX2+12

TD4-

TX4-

13 NB_LAN_TX2+

1 75_0402_1%

1:1

16

1 75_0402_1%

TXCT4 TX4+

1 75_0402_1%

TXCT3

TDCT4 TD4+

1 75_0402_1%

TDCT3

1

1

10 SW_LAN_TX2-11

2

5 SYS_LED_MASK#

CL21 0.47U_0603_10V7K

QL1B DMN66D0LDW-7_SOT363-6 4 3 LED_100_ORG#

9

<35,39>

CL20 0.47U_0603_10V7K

SW_100_ORG#

SYS_LED_MASK#

2

SYS_LED_MASK#

MHPC_NS692417 QL2A DMN66D0LDW-7_SOT363-6 LED_10_GRN# 1 6 1 CL22

2 EMC@ 150P_1808_2.5KV8J

RL18 2

RL17 2

RL16 2

GND CHASSIS

SYS_LED_MASK#

RL15 2

A

2

SW_10_GRN#

+GND_CHASSIS use 40mil trace if necessary


QL2B DMN66D0LDW-7_SOT363-6 4 3

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

5

A

Title

LAN Size

4

3

2

Rev 0.3

LA-A901P Date:

5


Sheet 1

28

of

53

A

B

+3.3V_MMI

C

D

E

CR3 close to UR1.9 CR1 CR2 close to UR1.27

1 2

1 2

2

1 2

1 2

CR3 0.1U_0402_25V6

CR2 0.1U_0402_25V6

CR6 0.1U_0402_25V6

CR4 0.1U_0402_25V6

1

CR1 4.7U_0603_6.3V6K

CR4 close to UR1.42 CR6 close to UR1.23

1

+3.3V_MMI

1

+3.3V_MMI

1

<11> <11>

PCIE_PRX_MMITX_P1 PCIE_PRX_MMITX_N1

CR26 1 CR27 1

2

RR2 2 0.1U_0402_10V7K 2 0.1U_0402_10V7K

2 0.1U_0402_10V7K 2 0.1U_0402_10V7K <7> <7>

RR6 100K_0402_5%

1

+3.3V_MMI

PE_REXT 2 191_0402_1% PCIE_PTX_MMIRX_P1_C PCIE_PTX_MMIRX_N1_C PCIE_PRX_MMITX_P1_C PCIE_PRX_MMITX_N1_C

<7,12>

IO_LDOSEL

PLTRST_MMI#

1

@ RR8 100K_0402_5%

2

14

17

MMICLK_REQ#

2 MEDIACARD_PWREN 10K_0402_5%

7 8

16

MEDIACARD_IRQ#

IO_LDOSEL

1 RR15

6 5

15 MEDIACARD_PWREN

<12>

4

2 3

CLK_PCIE_MMI# CLK_PCIE_MMI

<9>

+3.3V_MMI

18

SD_SKT_33VOUT

MAIN_LDO_VIN

SD_SKT_18VOUT

22

+3.3V_RUN_CARD

24

+1.8V_RUN_CARD

1

+1.8V_RUN_CARD

1

1 2

AUX _33VIN

2

SD_SKT_33VIN

1

2

SD_33VCCD

2

+3.3V_RUN_CARD

2

MAIN_LDO_12VOUT

CR31 near UR1.22 CORE_12VCCD SD_WPI SD_CD#

UHSII_12VCCAIN/NC UHSII_12VCCAIN/NC UHSII_12VCCAIN/NC

SD_CLK SD_CMD

PE_12VCCAIN MMC_D7 MMC_D6 MMC_D5 MMC_D4 SD_D3 SD_D2 SD_D1 SD_D0

PE_REXT PE_RXP PE_RXM PE_TXP PE_TXM

SD_RCLK_M/NC SD_RCLK_P/NC SD_D1P/NC SD_D1M/NC SD_D0M/NC SD_D0P/NC

PE_REFCLKM PE_REFCLKP PE_RST#_GATE# MAIN_LDO_EN

SD_REXT/NC

20 21

SDWP SD/MMCCD#

43 45

SD/MMCCLK_R SD/MMCCMD

RR1

1 EMC@ 2 10_0402_5%

39 40 44 46 47 48 37 38

SD/MMCDAT3 @EMC@ RR3 1 SD/MMCDAT2 @EMC@ RR4 1 SD/MMCDAT1 SD/MMCDAT0

29 30 32 33 34 35

SD_UHS2_D1P SD_UHS2_D1N SD_UHS2_D0N SD_UHS2_D0P

26

SD_REXT 1 RR5

2 0_0402_5% 2 0_0402_5%

CR34 near UR1.24

SD/MMCCLK

1

2 1

2 1

2 1

1

+SD_IO_LDO

1

1

1

2 2 1

2 1

1

36 31 28

+AUX_LDO

SD/MMCDAT3_R SD/MMCDAT2_R

EMI solution for SD card

@EMC@ CR23 5P_0402_50V8C

CR22 0.1U_0402_25V6

CR21 0.1U_0402_25V6

CR19 0.1U_0402_25V6

CR18 4.7U_0603_6.3V6K

2

41

12 25

2

11 10

CR24 1 CR25 1

AUX_LDO_CAP

CR34 4.7U_0603_6.3V6K

13

PCIE_PTX_MMIRX_P1 PCIE_PTX_MMIRX_N1

OZ777FJ2LN

CR31 1U_0402_6.3V6K

23

If RTD3 cold the AUX and MAIN power rail should be use different power rail; for RTD3 hot please keep this circuit

<11> <11>

UHSII_33VCCAIN/NC

SD_IO_LDO_CAP 42

+1.2V_LDO

2

PE_33VCCAIN

CR17 1U_0402_6.3V6K

2

27

CR15 0.1U_0402_25V6

1

9

CR14 4.7U_0603_6.3V6K

CR10 0.1U_0402_25V6

CR13 0.1U_0402_25V6

CR9 4.7U_0603_6.3V6K

CR8 0.1U_0402_25V6

CR7 4.7U_0603_6.3V6K

2

UR1 +1.2V_LDO

2

EMI depop location

2 4.7K_0402_1%

DEV_WAKE# CLKREQ#

LED#

IO0_LDOSEL

GND

19 49

OZ777FJ2LN_QFN48_6X6

please routing daisy chain 1. from UR1.38 (SD_D0) -> UR1.30 (SD_RCLK_P) -> LR3.4 2. From UR1.37 (SD_D1) -> UR1.29 (SD_RCLK_N) -> LR3.1 R231,R297,R306,R315,R333,R337 for EMI solution

3

3

+3.3V_RUN

+3.3V_MMI

PJP26

1

2 PAD-OPEN1x2m

JSD1

2

1 2

CR35 0.1U_0402_25V6

RR11 1M_0402_5%

1

+3.3V_RUN_CARD +1.8V_RUN_CARD

SD/MMCCMD SD/MMCCLK

4 14 2 5

SD/MMCCD# SDWP

18 19

SD/MMCDAT0 SD/MMCDAT1 SD/MMCDAT2_R SD/MMCDAT3_R SD_UHS2_D0P SD_UHS2_D0N SD_UHS2_D1P SD_UHS2_D1N

7 8 9 1 11 12 16 15 3 6 10 13 17

CONN@

VDD/VDD1 VDD2 CMD CLK CARD DETECT WRITE PROTEC DAT0/RCLK+ DAT1/RCLKDAT2 CD/DAT3 D0+ DOD1+ D1VSS1 VSS2 VSS3 VSS4 VSS5

20 21 22 23 24 25 26

GND1 GND2 GND3 GND4 GND5 GND6 GND7

ALPS_SCDADA0101_NR 4

4

DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. A

B

C

D

Title

Card Reader Size

Document Number

Date:


LA-A901P Sheet E

Rev 0.3 29

of

53

5

4

+3.3V_WWAN

3

NGFF slot B Key B 2

mSATA_DEVSLP 10K_0402_5% WWAN_PWR_EN 0_0402_5%

NGFF slot A Key A

NGFF for UMA

+3.3V_WLAN +3.3V_WWAN

JNGFF1

1 3 5 7

JNGFF2 <35>

<11> <11>

D

<35>

<6> <6> <6> <6>

PCIE_PTX_SATARX_N6_L1 PCIE_PTX_SATARX_P6_L1

PCIE_PTX_SATARX_N6_L0 PCIE_PTX_SATARX_P6_L0

USBP7+ USBP7-

NGFF_CONFIG_0 <35> WWAN_WAKE#

PCIE_PRX_SATATX_N6_L1 PCIE_PRX_SATATX_P6_L1 20.1U_0402_10V7K PCIE_PTX_SATARX_N6_L1_C 20.1U_0402_10V7K PCIE_PTX_SATARX_P6_L1_C

CZ32 1 CZ33 1 <6> <6>

<6> <6>

1 3 5 7 9 11

NGFF_CONFIG_3

PCIE_PRX_SATATX_P6_L0 PCIE_PRX_SATATX_N6_L0

20.1U_0402_10V7K PCIE_PTX_SATARX_N6_L0_C 20.1U_0402_10V7K PCIE_PTX_SATARX_P6_L0_C

CZ58 1 CZ59 1

<7> <7>

CLK_PCIE_SATA# CLK_PCIE_SATA

<35>

NGFF_CONFIG_1

<35>

NGFF_CONFIG_2

13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67

1 3 5 7 9 11

2 4 6 8 10

2 4 6 8 10

12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66

12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66

13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67

<11> <11>

WWAN_PWR_EN WWAN_RADIO_DIS#_R WWAN_LED#

HW_GPS_DISABLE2#_R UIM_RESET UIM_CLK UIM_DATA

1 CV145 1 CV146 1 CV147 1 CV148

<25> <25>

WIGIG_LANE_N3 WIGIG_LANE_P3

<25> <25>


<11> <11>

PCIE_PTX_WLANRX_P4 PCIE_PTX_WLANRX_N4

USBP2+ USBP2-

2 2 0.1U_0402_25V6 0.1U_0402_25V6 2 2 0.1U_0402_25V6 0.1U_0402_25V6

WIGIG_LANE_N3_C WIGIG_LANE_P3_C WIGIG_LANE_N2_C WIGIG_LANE_P2_C

<25> +SIM_PWR mSATA_DEVSLP

WIGIG_HPD 2 0.1U_0402_10V7K PCIE_PTX_WLANRX_P4_C 2 0.1U_0402_10V7K PCIE_PTX_WLANRX_N4_C

CZ13 1 CZ14 1

<12> <11> <11>

PCIE_PRX_WLANTX_P4 PCIE_PRX_WLANTX_N4 <7> <7>

PCH_PLTRST#_EC SATACLK_REQ#

PCIE_WAKE#

<7>

CLK_PCIE_WLAN CLK_PCIE_WLAN#

<7,12> WLANCLK_REQ# <35> PCIE_WAKE# <11> <11>

2 0.1U_0402_10V7K PCIE_PTX_WIGIGRX_P5_C 2 0.1U_0402_10V7K PCIE_PTX_WIGIGRX_N5_C

CZ21 1 CZ22 1

PCIE_PTX_WIGIGRX_P5 PCIE_PTX_WIGIGRX_N5

<11> <11>

PCIE_WAKE#

PCIE_PRX_WIGIGTX_P5 PCIE_PRX_WIGIGTX_N5 <7> <7>

CLK_PCIE_WIGIG CLK_PCIE_WIGIG#

1 3 5 7

9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67

GND

2

+

2

WIGIG_AUX#_C WIGIG_AUX_C 0.1U_0402_25V6 0.1U_0402_25V6 WIGIG_LANE_N1_C WIGIG_LANE_P1_C 0.1U_0402_25V6 0.1U_0402_25V6 WIGIG_LANE_N0_C WIGIG_LANE_P0_C 0.1U_0402_25V6 0.1U_0402_25V6

2 2

1 1CV150 CV149 1 1CV152 CV153 1 1CV156 CV157

2 2 2 2

WIGIG_AUX# <25> WIGIG_AUX <25>

D


<25> <25>


<25> <25>

PCH_CL_RST1# <7> PCH_CL_DATA1 <7> PCH_CL_CLK1 <7>

WIGIG_32KHZ PCH_PLTRST#_EC PCH_PLTRST#_EC BT_RADIO_DIS#_R WLAN_WIGIG60GHZ_DIS#_R

<9,27,35,36>

PCH_PLTRST#_EC WIGIGCLK_REQ#

PCIE_WAKE#

<7,12>

68

5

C

@

1

BT_LED#

8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66

+3.3V_ALW

AUX_EN_WOWL <35,36> <35>

1

WWAN_RADIO_DIS#

2

EC_32KHZ_MEC5085

WWAN_RADIO_DIS#_R

2

1

UZ11

B A

Y 3

1

1 2

2

1

1 2

2

1 2

CZ56 150U_6.3V_M

@

+

CZ57 150U_B2_6.3VM_R35M

CZ55 33P_0402_50V8J

CZ53 33P_0402_50V8J

CZ54 22U_0603_6.3V6M

1

WLAN_LED#

CONN@

conn should be change SP070011B00 TBD CZ52 0.047U_0402_16V4Z

CZ51 0.047U_0402_16V4Z

C

GND

2 4 6

BELLW_80148-3221

BELLW_80149-4221 CONN@ +3.3V_WWAN

GND

68

GND

8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66

9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67

69 69

2 4 6

P

2

1

G

1 @ RZ39 1 @ RZ43

2

<9>

1

SUSCLK

2 0_0402_5% 2 0_0402_5%

@ RZ56

WIGIG_32KHZ_R

4

1 RZ57

WIGIG_32KHZ

TC7SH08FU_SSOP5

DZ5 RB751S40T1G_SOD523-2 +3.3V_WLAN WLAN_WIGIG60GHZ_DIS#_R

CONFIG_2

CONFIG_3

Module Type

0

GND

GND

GND

GND

SSD-SATA

1

GND

HIGH

GND

GND

SSD-PCIE

8

HIGH

GND

GND

GND

WWAN

14

HIGH

GND

HIGH

HIGH

HCA-PCIE

<35>

BT_RADIO_DIS#

1

2

BT_RADIO_DIS#_R

1 2

2 1

2 1

1 2

2

CONFIG_1

CZ19 4.7U_0603_6.3V6K

STATE # CONFIG_0

CZ18 0.1U_0402_25V6

DZ1 RB751S40T1G_SOD523-2

1

2

CZ17 0.1U_0402_25V6


1

CZ16 0.047U_0402_16V4Z

WLAN_WIGIG60GHZ_DIS#

CZ20 0.047U_0402_16V4Z

<35>

2

HW_GPS_DISABLE2#_R

2

1

1

HW_GPS_DISABLE2#

@CZ15 0.1U_0402_25V6

<35>


Power Rating TBD PWR Rail

Primary Power

Voltage Tolerance

Peak

Aux Power

Normal

Normal

+3.3V B

15

HIGH

HIGH

HIGH

HIGH

NA

B

LED control circuit SIM Card

+3.3V_WLAN +3.3V_WLAN

GND

GND

8 10 12

1 2 <35>

AUX_EN_WOWL

AUX_EN_WOWL +5V_ALW

<36,42>

SUS_ON

T-SOL_159-1201300600

3 4 5 6 7

VIN1 VIN1

VOUT1 VOUT1

ON1

CT1

VBIAS

GND

ON2

CT2

VIN2 VIN2

VOUT2 VOUT2 GPAD

+3.3V_WLAN_UZ3 1 @ CZ36

2 0.1U_0402_10V7K

1 CZ37

2 470P_0402_50V7K

2

2

14 13 12

5

UZ3

1

+3.3V_ALW

BT_LED#

4

11 10 9 8

+3.3V_SUS_UZ3

1 CZ62 1 @ CZ63

2 470P_0402_50V7K 2 0.1U_0402_10V7K

15

WLAN_LED#

WIRELESS_LED#

1

6

QZ2A DMN66D0LDW-7_SOT363-6 +3.3V_WWAN

UIM_CLK

WWAN_LED#

1

UIM_RESET

RZ37 100K_0402_5%

+3.3V_SUS

2

1 PAD-OPEN1x1m

1

6

A

4 UIM_DATA

1

1 2

2

@EMC@ CZ67 33P_0402_50V8J

@EMC@ CZ66 33P_0402_50V8J

@EMC@ CZ65 33P_0402_50V8J

1

QZ11A DMN66D0LDW-7_SOT363-6

2

<35,39>

PJP17

2


A

3

QZ2B DMN66D0LDW-7_SOT363-6

5

GND

+SIM_PWR

2

VCC

GND

UIM_RESET

2

RST

GND

PJP12 PAD-OPEN1x1m

UIM_CLK

6

1

VPP

2 4

2

11

CLK

2

9

NC

I/O

C263 1U_0402_6.3V6K

7

NC

RZ15 100K_0402_5%

5

RZ14 100K_0402_5%

3

AUX_EN_WOWL 100K_0402_5%

1

JSIM1 CONN@

1 UIM_DATA

2

1

1 RZ38

3



For RF Team request 5

4

3

2

Title

NGFF Card Size

Document Number

Date:


Rev 0.3

LA-A901P Sheet 1

30

of

53

5

4

3

2

1

+USB_LEFT_PWR

7 7

USB3TN1_D-

5 5

6 6

USB3TP1_D+

3 3 8 L05ESDL5V0NA-4_SLP2510P8-10-9

EMC@ SW_USB3TN1

2

1

USB3TN1_C 0.1U_0402_10V7K

4

2

1

USB3TP1_C 0.1U_0402_10V7K

1

CI4 SW_USB3TP1 CI5

1

D

USB3RN1_DUSB3RP1_D+ 2

4 4

USB3TP1_D+

3

USB3TN1_D-

DLW21HN900HQ2L_4P

JUSB1

LI2

4

3

1

2

3

USB3TN1_D-

2

USB3TP1_D+

DLW21HN900HQ2L_4P

EMC@

SW_USBP0+

4

SW_USBP0-

1

LI3

4

3

1

2

1 2 3 4 5 6 7 8 9

USBP0_DUSBP0_D+

2

USB3RP1_D+

3

USBP0_D+

2

USBP0_D-

DLW21HN900HQ2L_4P

EMC@ DI2 AZC199-02SPR7G_SOT23-3

9 8

3

USB3RP1_D+

2 2

1

2

USB3RP1_D+

1

2

USB3RN1_D-

2

1

3

1

1

3

USB3RN1_D-

CI3 0.1U_0402_25V6

SW_USB3RP1

LI1

4

10 9

CI1 100U_1206_6.3V6M

4

DI1 EMC@ 1 1

2

EMC@

SW_USB3RN1

USB3RN1_D-

USB3TN1_DUSB3TP1_D+

CONN@

VBUS DD+ GND SSRXSSRX+ GND SSTXSSTX+

10 11 12 13

GND GND GND GND

C-K_26210-8K1A-02 D

+USB_LEFT_PWR

+5V_ALW

OE# <26,28,35>

10 32

DOCKED

SS_SEL HS_SEL

GND GND HGND

25 24 23 22 15 14 13

H12 Entry DOCK_USB3TP1 <34> DOCK_USB3TN1 <34> DOCK_USB3RP1 <34> DOCK_USB3RN1 <34> DOCK_USBP0+ <34> DOCK_USBP0- <34>

11 21 28 33

Dock M/B

NA

2

<11,12>

ESD Request +5V_ALW

NA

H14 DSC USB3102 NX3DV221 1

H14 UMA USB3102 NX3DV221 H14D_En

NA

NA

H14U_En

NA

NA

2

C

Close to JUSB1 (Place on TOP)

H15 UMA USB3102 NX3DV221

function

0

USB_OC0#

SY6288D10CAC_MSOP8

H15 DSC USB3102 NX3DV221

check port mapping 1

USB2 3

USB_PWR_EN1#

8 7 6 5

H12 UMA USB3102 NX3DV221

PI3USB3102ZLEX_TQFN32_6X3

DOCKED

USB2 0

<35>

GND VOUT VIN VOUT VIN VOUT EN FLG

@EMC@ CI421 22U_0603_6.3V6M

TX+B TX-B RX+B RX-B D+B D-B USB_IDB

TX+ TXRX+ RXD+ DUSB_ID

SW_USB3TP1 SW_USB3TN1 SW_USB3RP1 SW_USB3RN1 SW_USBP0+ SW_USBP0-

31 30 27 26 19 18 17

2

1 1 2

1 2

1 2

1 2

1 2

1 2

1 2

TX+A TX-A RX+A RX-A D+A D-A USB_IDA

CI7 0.1U_0402_25V6

CI416 0.1U_0402_25V6

CI414 0.1U_0402_25V6

@ CI417 0.1U_0402_25V6

CI415 0.1U_0402_25V6

@ CI418 0.1U_0402_25V6

@ CI419 0.1U_0402_25V6

CI420 4.7U_0603_6.3V6K

C

VDD VDD VDD VDD VDD VDD

1 2 4 5 6 7 8

<11> USB3TP1 <11> USB3TN1 <11> USB3RP1 <11> USB3RN1 <11> USBP0+ <11> USBP0-

PCB

UI4 3 9 12 16 20 29

@ CI6 10U_0603_6.3V6M

+3.3V_SUS

1

UI1 1 2 3 4

H15D_En

NA

NA

H15U_En

NA

NA +USB_RIGHT_PWR JUSB2

USB3RN4_D-

USB3TN4

<11>

USB3TP4

1

USB3TN4_C 0.1U_0402_10V7K

2

1

USB3TP4_C 0.1U_0402_10V7K

CI27

4

USB3RN4_D-

9 8

USB3RP4_D+

USB3TN4_D-

4 4

7 7

USB3TN4_D-

USB3TP4_D+

5 5

6 6

USB3TP4_D+

1

2

4

3

2

USB3TN4_D-

3

USB3TP4_D+

1

3 3

EMC@

USB3RN4_DUSB3RP4_D+ 3

10 9

2 2

1

2 CI28

1 1

USB3RP4_D+

8 L05ESDL5V0NA-4_SLP2510P8-10-9


<11>

LI8 1

USB3RN4_D-

1

USB3RP4_D+

3

3

2

4

DLW21HN900HQ2L_4P

CI10 0.1U_0402_25V6

4

USB3RP4

CI8 100U_1206_6.3V6M

DI6 EMC@ <11>

1 2 3 4 5 6 7 8 9

USBP3_DUSBP3_D+

2

2

2

3

1

2

USB3RN4

1

<11>

EMC@

2

LI9 1

B

USB3TN4_DUSB3TP4_D+

CONN@


B

GND GND GND GND

10 11 12 13

C-K_26210-8K1A-02

DLW21HN900HQ2L_4P +USB_RIGHT_PWR

+5V_ALW

1

CI38 0.1U_0402_25V6

2

<35> DOCKED_LIO_EN <11> USBP3+ <11> USBP3-

10 9 8 7 6

VCC S D+ DOE#

1D+ 1D2D+ 2DGND

1 2 3 4 5

SW_USBP3+ SW_USBP3-

4

3

2

USBP3_D+

3

USBP3_D-

DLW21HN900HQ2L_4P DOCK_USBP3+ DOCK_USBP3-

2

4

2

1

SW_USBP3-

EMC@ 1

2

LI4 1

CI12 0.1U_0402_25V6

UI5

A

SW_USBP3+

APR/SPR/LIO Dock

@ CI11 10U_0603_6.3V6M

+3.3V_SUS

1

UI2

<35>

1 2 3 4

USB_PWR_EN2#

8 7 6 5

USB_OC2#

<11,12>

SY6288D10CAC_MSOP8

<34> <34>

A

NX3DV221GM_XQFN10U10_2X1P55


check port mapping DOCKED_LIO_EN


function

1

Dock

0

M/B

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

Title

USB3.0 Size

4

3

2

Document Number

Rev 0.3

LA-A901P Date:

5

GND VOUT VIN VOUT VIN VOUT EN FLG


Sheet 1

31

of

53

4

3

USB3RN2_D-

3

USB3RP2_D+

USB3RN2_D-

<11>

USB3TP2

2 CI16

USB3TP2_C 1 0.1U_0402_10V7K

LI5 1 4

EMC@ 1

2

4

3

2

USB3TN2_D-

3

USB3TP2_D+

USB3RP2_D+

USB3TN2_D-

4 4

7 7

USB3TN2_D-

USB3TP2_D+

5 5

6 6

USB3TP2_D+

3 3 8

1

2

1

2

L05ESDL5V0NA-4_SLP2510P8-10-9

DLW21HN900HQ2L_4P

+5V_ALW

USB3RN2_DUSB3RP2_D+


USB3TN2_C 1 0.1U_0402_10V7K

9 8

1 2 3 4 5 6 7 8 9

USBP1_R_DUSBP1_R_D+ CI17

2 CI13

2 2

JUSB3

CI14

USB3TN2

USB3RN2_D0.1U_0402_25V6

<11>

10 9

100U_1206_6.3V6M

USB3RP2_D+

DLW21HN900HQ2L_4P

DI4 EMC@ 1 1

2

4

+5V_USB_CHG_PWR

2

2

USB3RP2

D

2

3

4

EMC@ 1

1

3

<11>

LI6 1

USB3RN2

2

1

<11>

3

1

5

USB3TN2_DUSB3TP2_D+


D

GND GND GND GND

10 11 12 13

SINGA_2UB1641-000111F CONN@

+5V_USB_CHG_PWR UI3 1

+5V_ALW

2

CI19 0.1U_0402_25V6

1

<11> <11> <11,12>

<35>

USB_PWR_SHR_VBUS_EN

FAULT#

4

LI7 PS_USBP1_D-

DP_IN DM_IN

10 11

EN

6 7 8

CTL1 CTL2 CTL3

+5V_ALW

4

PS_USBP1_D+ PS_USBP1_DPS_USBP1_D+

1

EMC@ 4 1

3 2

3

USBP1_R_D-

ESD Request

2

USBP1_R_D+

+5V_ALW

DLW21HN900HQ2L_4P ILIM_LO ILIM_HI NC GND GNDP

15 16

RI14

2

C

1 22.1K_0402_1% 1

9 14 17

2

TPS2544RTER_WQFN16_3X3 RI13

@EMC@ CI422 22U_0603_6.3V6M

USB_PWR_SHR_EN#

12

ILIM_SEL

5

CI19 near UI3.1 <35,36>

OUT

DM_OUT DP_OUT

13

USB_OC1# ILIM_SEL

C

IN

2 3

USBP1USBP1+

ILIM_SEL 1 10K_0402_5%

2

Close to JUSB3 (Place on TOP)

B

B

A

A


4

3

2

Title

USB SW Size

Document Number

Date:


Rev 0.3

LA-A901P Sheet 1

32

of

53

5

4

3

2

1

D

D

Houston 14 NFC on USH

C

C

B

B

A

A


Title

NFC Size

4

3

2

Rev 0.3

LA-A901P Date:

5


Sheet 1

33

of

53

5

4

3

2

1

JDOCK1

EMC@ R265 1 EMC@ R266 1

2 33_0402_5% DPC_DOCK_LANE_P3 2 33_0402_5% DPC_DOCK_LANE_N3

<25> <25>

2

Close to DOCK Its for Enhance ESD on dock issue.

+NBDOCK_DC_IN_SS

@EMC@ C310 0.033U_0402_16V7K

1

DPC_DOCK_HPD

1

<26>

RED_DOCK

RED_DOCK GREEN_DOCK

GREEN_DOCK

<26> <26>

HSYNC_DOCK VSYNC_DOCK

<36> <36>

CLK_MSE DAT_MSE

R268 100K_0402_5%

2

BLUE_DOCK

<26>

DPC_DOCK_HPD

C

<26>

BLUE_DOCK

<21> <21>

DAI_BCLK# DAI_LRCK#

<21> <21>

DAI_DI DAI_DO#

<21>

DAI_12MHZ#

<35> <35>

D_LAD2 D_LAD3

<35> D_LFRAME# <35> D_CLKRUN#

<7>

<36>

<36> DOCK_SMB_CLK DOCK_SMB_DAT

<35,40> <36> <35,40,47>

B

CLK_PCI_DOCK

DOCK_SMB_ALERT# <40> DOCK_PSID

DOCK_PWR_BTN# SLICE_BAT_PRES#

SLICE_BAT_PRES#

2

3

PWR2 PWR2 PWR2 GND2

Shield_G Shield_G Shield_G Shield_G Shield_G Shield_G

Shield_G Shield_G Shield_G Shield_G Shield_G Shield_G

ACAV_DOCK_SRC#

<47>

DAT_DDC2_DOCK <26> CLK_DDC2_DOCK <26> SATA_PRX_DKTX_P0 SATA_PRX_DKTX_N0 SATA_PTX_DKRX_P0 SATA_PTX_DKRX_N0

2 C312 2 C313 1 C314 1 C315

1 1 0.01U_0402_16V7K 0.01U_0402_16V7K 2 2 0.01U_0402_16V7K 0.01U_0402_16V7K

DPB_LANE_P3 <22> DPB_LANE_N3 <22>

CLK_KBD DAT_KBD

DPB_DOCK_HPD

<22>

Close to DOCK Its for Enhance ESD on dock issue.

SATA_PRX_DKTX_P0_C <6> SATA_PRX_DKTX_N0_C <6> SATA_PTX_DKRX_P0_C <6> SATA_PTX_DKRX_N0_C <6> DOCK_USBP3+ DOCK_USBP3-

DOCK_USBP0+ DOCK_USBP0-

<31> <31>

<31> <31>

<36> <36>

C

DOCK_USB3RN1 DOCK_USB3RP1

<31> <31>

DOCK_USB3TN1 DOCK_USB3TP1

<31> <31>

EMI solution for E-Docking USB DPB_DOCK_HPD

BREATH_LED# <36,39> DOCK_LOM_ACTLED_YEL# DOCK_LOM_TRD0+ DOCK_LOM_TRD0-

<28> <28>


<28> <28>

<28>

+3.3V_ALW2 +LOM_VCT

+LOM_VCT DOCK_LOM_TRD2+ <28> DOCK_LOM_TRD2- <28> DOCK_LOM_TRD3+ <28> DOCK_LOM_TRD3- <28> DOCK_DCIN_IS+ DOCK_DCIN_ISDOCK_POR_RST# DOCK_DET_R#

DOCK_DET# 1 100K_0402_5%

2 R272

<46> <46>

<36> 1

D19 2

DOCK_DET#

<35,47>

B

RB751S40T1G_SOD523-2 +DOCK_PWR_BAR

DAI_12MHZ#

EMC@ C319 4.7P_0402_50V8C

1

CLK_PCI_DOCK EMC@ R273 10_0402_5%

2

DAI_BCLK# EMC@ EMC@ C42 R6 4.7P_0402_50V8C 10_0402_5%

EMC@ EMC@ C43 R41 4.7P_0402_50V8C 10_0402_5%

JAE_WD2F144WB5R400 CONN@

DPB_DOCK_HPD

149 150 151 152 159 160 161 162 163 164


DPB_DOCK_AUX <25> DPB_DOCK_AUX# <25>

2

1

1 2

2

153 154 155 156 157 158

GND1 PWR1 PWR1 PWR1

DPB_DOCK_AUX DPB_DOCK_AUX#

C318 0.1U_0603_50V7K

D20 @EMC@ L30ESD24VC3-2_SOT23-3

C317 0.1U_0603_50V7K

@ C33 4.7U_0805_25V6-K

1

+DOCK_PWR_BAR

145 146 147 148

1 0.1U_0402_10V7K 1 0.1U_0402_10V7K

@ C316 1U_0402_6.3V6K

<35> D_SERIRQ <35> D_DLDRQ1#

C308 2 C309 2

D

R271 100K_0402_5%

<35> D_LAD0 <35> D_LAD1

2 33_0402_5% DPB_LANE_P3_C 2 33_0402_5% DPB_LANE_N3_C

@EMC@ C311 0.033U_0402_16V7K

<22>

DPC_DOCK_AUX DPC_DOCK_AUX#

DPC_DOCK_AUX DPC_DOCK_AUX# DPC_DOCK_HPD

DPB_DOCK_LANE_P3 EMC@ R258 1 DPB_DOCK_LANE_N3 EMC@ R267 1


1

DPC_LANE_P3_C DPC_LANE_N3_C


2

1 0.1U_0402_10V7K 1 0.1U_0402_10V7K

1 0.1U_0402_10V7K 1 0.1U_0402_10V7K

1

C300 2 C301 2

C305 2 C307 2

2

<22> DPC_LANE_P3 <22> DPC_LANE_N3


1



2


1 0.1U_0402_10V7K 1 0.1U_0402_10V7K

1

EMC@ R257 1 EMC@ R263 1

C298 2 C303 2

2


1 0.1U_0402_10V7K 1 0.1U_0402_10V7K


1

1 0.1U_0402_10V7K 1 0.1U_0402_10V7K

C294 2 C296 2


2

C304 2 C306 2

DOCK_AC_OFF <47> DOCK_LOM_SPD100LED_ORG# <28> DPB_CA_DET <22,25> DPB_DOCK_LANE_P0 EMC@ R260 1 2 33_0402_5% DPB_LANE_P0_C DPB_DOCK_LANE_N0 EMC@ R261 1 2 33_0402_5% DPB_LANE_N0_C DPB_CA_DET

1

EMC@ R253 1 EMC@ R255 1

DOCK_AC_OFF

2


2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144

1

1 0.1U_0402_10V7K 1 0.1U_0402_10V7K


2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144

2

C297 2 C299 2


1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143

1


C302 2 C295 2

<22> DPC_LANE_P0 <22> DPC_LANE_N0 D

1 0.1U_0402_10V7K 1 0.1U_0402_10V7K

DOCK_LOM_SPD10LED_GRN# DPC_CA_DET <22,25> DPC_CA_DET 2 33_0402_5% DPC_DOCK_LANE_P0 EMC@ R259 1 2 33_0402_5% DPC_DOCK_LANE_N0 EMC@ R252 1

1

<28>

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143

2

DOCK_DET_1

EMI depop location

A

A


4

3

2

Title

E-Dock Size

Document Number

Date:


Rev 0.3

LA-A901P Sheet 1

34

of

53

5

4

3

2

1

+3.3V_ALW +3.3V_ALW

+3.3V_ALW_UE1 PJP14

1

2

+3.3V_ALW

2

1 RE12

1 @ RE83

<34,40>

DOCK_SMB_ALERT# @ T96 PAD~D

<31> USB_PWR_EN2# <21> EN_I2S_NB_CODEC# <27> USH_PWR_STATE# <47> EN_DOCK_PWR_BAR <30> HW_GPS_DISABLE2# <23> _BKEN_EC <23> LCD_TST <40> PSID_DISABLE# <26,28,31> DOCKED <34,47> DOCK_DET# <21> AUD_NB_MUTE# <28> 3.3V_WWAN_EN <23> LCD_VCC_TEST_EN <30> WWAN_WAKE# <21> AUD_HP_NB_SENSE <31> USB_PWR_EN1#

C

<47> SLICE_BAT_ON <34,40,47> SLICE_BAT_PRES# @ T97 PAD~D @ T99 PAD~D

1

2

RE21

1 RE20

SYS_LED_MASK# 10K_0402_5%

2

<30>

LCD_TST 100K_0402_5%

WLAN_WIGIG60GHZ_DIS# <36> EC5048_TX @ T98 PAD~D

<27>

USB_PWR_EN2#

HW_GPS_DISABLE2# LCD_TST

WWAN_WAKE# USB_PWR_EN1#

SLICE_BAT_ON SLICE_BAT_PRES# EXPRESS_DET# SMART_DET#

WLAN_WIGIG60GHZ_DIS# USB_DB_DET#

BCM5882_ALERT#

VGA_ID

+3.3V_ALW <28,39> VGA_ID 1 100K_0402_5% VGA_ID 1 @ 100K_0402_5%

B

2 RE84 2 RE85

VGA_ID0 0

UMA

1

<30> <30> <9>

BT_RADIO_DIS# WWAN_RADIO_DIS#

USB_PWR_SHR_VBUS_EN

BT_RADIO_DIS# WWAN_RADIO_DIS#

SIO_SLP_WLAN#

B32 A31 B33 B15 A15 B16 A16 A1 B2 A2 B3 A3 B45 A42 B4 A59 B62 A58 B61 A56 B59 A55 B58 B47 A45 B48 A46 B49 A47 B50 A48 B13 A13 A53 B57 B14 A14 B17 B18

1 2

1 2

1 2

1 2

1 2

GPIOJ0 GPIOJ1/TACH1 GPIOJ2/TACH2 GPIOJ3 GPIOJ4 GPIOJ5 GPIOJ6 GPIOJ7

GPIOB0 GPIOB1 GPOC2 GPOC3 GPOC4 GPOC5 GPOC6/TACH4 GPIOC7 GPIOD0 GPIOC1 GPIOC0 GPIOB7 GPIOB6 GPIOB5 GPIOB4 GPIOB3 GPIOB2

GPIOK0 GPIOK1/TACH3 GPIOK2 GPIOK3 GPIOK4 GPIOK5 GPIOK6 GPIOK7 GPIOL0/PWM7 GPIOL1/PWM8 GPIOL2/PWM0 GPIOL3/PWM1 GPIOL4/PWM3 GPIOL5/PWM2 GPIOL6 GPIOL7/PWM5

GPIOD1 GPIOD2 GPIOD3 GPIOD4 GPIOD5 GPIOD6 GPIOD7

GPIOM1 GPIOM3/PWM4 GPIOM4/PWM6

GPIOE0/RXD GPIOE1/TXD GPIOE2/RTS# GPIOE3/DSR# GPIOE4/CTS# GPIOE5/DTR# GPIOE6/RI# GPIOE7/DCD# GPIOF0 GPIOF1 GPIOF2 GPIOF3/TACH8 GPIOF4/TACH7 GPIOF5 GPIOF6 GPIOF7

1

2

1

RE35

D

RE276

LAD0 LAD1 LAD2 LAD3 LFRAME# LRESET# PCICLK CLKRUN# LDRQ1# SER_IRQ 14.318MHZ/GPIOM0 CLK32/GPIOM2 DLAD0 DLAD1 DLAD2 DLAD3 DLFRAME# DCLKRUN# DLDRQ1# DSER_IRQ

GPIOG0/TACH5 GPIOG1 GPIOG2 GPIOG3 GPIOG4 GPIOG5 GPIOG6 GPIOG7/TACH6

BC_INT# BC_DAT BC_CLK

GPIOH0 GPIOH1 SYSOPT1/GPIOH2 SYSOPT0/GPIOH3 GPIOH4 GPIOH5 GPIOH6 GPIOH7

RPE8

SATA2_PCIE6_L1

A8 B9 B10 A10 B11 A11 B12 A12 B60 A57 B64 B68 A9 B1 A18 A44 B34 B39 B51 A27 A26 B26 B25 A21 B22 A28 B20 A22 B21 A32 B35 B29 B28 A25 A24 B23 A19 B24 A20

<6,12>

DOCK_AC_OFF_EC

B67 A64 A5 B6 A6 B7 A7 B8

D_DLDRQ1# LPC_LDRQ1# D_SERIRQ D_CLKRUN#

AUX_EN_WOWL

1 2 3 4

8 7 6 5

100K_0804_8P4R_5%

<47>

<30> PCIE_WAKE#

GPIO_PSID_SELECT DOCK_HP_DET DOCK_MIC_DET

PCIE_WAKE#_R

<21> <21>

MASK_SATA_LED#

PCIE_WAKE#_R 2 @ RE275

<39>

LED_SATA_DIAG_OUT# NGFF_CONFIG_0

NGFF_CONFIG_0

<39>

1 0_0402_5%

2 @ RE274

PCH_PCIE_WAKE#

<9,36>

Stuff RE275 and no stuff RE274 keep E5 design Stuff RE274 and no stuff RE275 to save two GPIOs on EC(PCH_PCIE_WAKE# should be output with OD)

SLICE_BAT_ON 2 RE17

NGFF_CONFIG_3

1 0_0402_5%

<30>

WLAN_LAN_DISBL# NGFF_CONFIG_1 NGFF_CONFIG_2

<30>

<40>

1 100K_0402_5%

C

<28>

NGFF_CONFIG_1 NGFF_CONFIG_2

<30> <30>

NGFF_CONFIG_3

<30>

DIS_BAT_PROCHOT#

<47>

LPC_LAD0 <7,36> LPC_LAD1 <7,36> LPC_LAD2 <7,36> LPC_LAD3 <7,36> LPC_LFRAME# <7,36> PCH_PLTRST#_EC <9,27,30,36> CLK_PCI_SIO <7> CLKRUN# <9,12,36>

CLK_PCI_SIO CLKRUN# LPC_LDRQ1#

IRQ_SERIRQ

<12,36>

EC_32KHZ_MEC5085

<30,36>

D_LAD0 <34> D_LAD1 <34> D_LAD2 <34> D_LAD3 <34> D_LFRAME# <34> D_CLKRUN# <34> D_DLDRQ1# <34> D_SERIRQ <34>

D_CLKRUN# D_DLDRQ1# D_SERIRQ

A29 B31 A30

BC_INT#_ECE5048 BC_DAT_ECE5048 BC_CLK_ECE5048

B

<36> <36> <36> +3.3V_ALW

PWRGD OUT65 TEST_PIN

VSS EP

RUNPWROK

<9,36>

B19 B46

2 10K_0402_5%

+CAP_LDO trace width 20 mils

LID_CL_SIO#

2 RE26

1

LID_CL#

10_0402_5%

<39>

CLK_PCI_SIO

1 2 A

CE8 0.047U_0402_16V4Z

2

B27 C1

1 RE24 +CAP_LDO

@EMC@ CE9 @EMC@ RE27 33P_0402_50V8J 33_0402_5%

DB Version 0.4 ECE5048-LZY_DQFN132_11X11~D

RUNPWROK

CE7 4.7U_0603_6.3V6K

CAP_LDO

A4 B56

RE25 100K_0402_5%

Discrete

<32>

SYS_LED_MASK#

<30,39> WIRELESS_LED# USB_PWR_SHR_VBUS_EN

SYS_LED_MASK#

A33 B36 A34 B37 A35 B38 A36 A37 B40 A38 B41 A39 B42 A40 B43 A41 B44

B5 A17 B30 A43 A54

2 PROCHOT_GATE LID_CL_SIO# DOCK_SMB_ALERT# TOUCH_SCREEN_PD#

A23 B63 A60 A61 B65 A62 B66 A63

1

BT_RADIO_DIS# 100K_0402_5% HW_GPS_DISABLE2# 2 100K_0402_5% PROCHOT_GATE 2 100K_0402_5%

1 RE11

LAN_DISABLE#_R

2

+3.3V_RUN

GPIOI0 GPIOI1 GPIOI2/TACH0 GPIOI3 GPIOI4 GPIOI5 GPIOI6 GPIOI7

2

100K_0804_8P4R_5%

<28>

GPIOA0 GPIOA1 GPIOA2 GPIOA3 GPIOA4 GPIOA5 GPIOA6 GPIOA7

1

NGFF_CONFIG_0 NGFF_CONFIG_1 NGFF_CONFIG_2 NGFF_CONFIG_3

B52 A49 B53 A50 B54 A51 B55 A52

WWAN_WAKE# 10K_0402_5%

2

1 2 3 4

DOCKED_LIO_EN

PCIE_WAKE#_R 10K_0402_5%

1

RPE4

8 7 6 5

<31>

1

1 RE9

2

1 RE8

UE1

VCC1 VCC1 VCC1 VCC1 VCC1

1 RE10

CE6 0.1U_0402_25V6

RE5

CE5 0.1U_0402_25V6

D

2

CE4 0.1U_0402_10V7K

SLICE_BAT_PRES# 100K_0402_5% WWAN_RADIO_DIS# 2 100K_0402_5% 2 WLAN_WIGIG60GHZ_DIS# 100K_0402_5% DOCK_SMB_ALERT# 2 100K_0402_5%

1

PAD-OPEN1x1m

CE3 0.1U_0402_25V6

<32,36>

CE2 0.1U_0402_25V6

USB_PWR_SHR_EN#

100K_0804_8P4R_5%

CE1 10U_0603_6.3V6M

1 USB_PWR_SHR_VBUS_EN USB_PWR_EN1# 2 USB_PWR_EN2# 3 4

1

RPE9

8 7 6 5

A


4

3

2

Title

ECE5048 Size

Document Number

Date:


Rev 0.3

LA-A901P Sheet 1

35

of

53

5

4

3

2

1

+RTC_CELL +3.3V_ALW 2

1 2 XTAL1 XTAL2

B66

2

2 REM_DIODE1_N REM_DIODE1_P REM_DIODE2_N REM_DIODE2_P REM_DIODE4_N REM_DIODE4_P

1 RE60 CE24 1

2 43_0402_5% 2 2200P_0402_50V7K

CE26 1

2 2200P_0402_50V7K

CE27 1

PECI_EC

<9>

2 0_0402_5%

+1.05V_RUN +3.3V_ALW RPE6

2 4.7K_0402_5%

PCH_RSMRST#

H_PROCHOT# I_BATT <46> I_SYS <46>

1 47K_0402_5%

2 RE88

<9,45,46>

JFAN1 1 2 3 4

U

GND1 GND2

DP2/DN2

DIMM

DN2a/DP2a

WiGig

DP4/DN4

V.R

1 2 3 4

FAN1_PWM FAN1_TACH +5V_RUN

5 6

ACES_50271-0040N-001 CONN@

1

1

1

2 1

C

3

E

2

2 B QE3 MMBT3904WT1G_SC70-3~D REM_DIODE1_N

THERMATRIP2#

1

+1.05V_RUN

1 RE70

DP2/DN2 for SODIMM on QE5, place QE5 close to SODIMM and CE37 close to QE5

E

H_THERMTRIP#

1

1 2

3

3 1

1

2

<12>

C

2 B E QE5 MMBT3904WT1G_SC70-3~D REM_DIODE2_N

2 B E QE6 MMBT3904WT1G_SC70-3~D

1 2

1

VSET_5085

2

1

2

C

3

2

QE7

1

1 2

1

2

THSEL_STRAP 1 RE78

RE77 1.58K_0402_1%

2

MMBT3904WT1G_SC70-3~D

REM_DIODE4_P

@ RE82 10K_0402_5%

1

2 2 2.2K_0402_5% B

DN2a/DP2a for WiGig on QE7, place QE7 close to WiGig and CE46 close to QE7

DP4/DN4 for Skin on QE6, place QE6 close to Vcore VR choke.

FWP#

2

C

3

1 2 6 1

+3.3V_ALW

REM_DIODE1_P

5

B

reserve for DC fan

Place under U Place CE35 close to the QE3 as possible

CE38 0.1U_0402_25V6

BOARD_ID CE40 4700P_0402_25V7K

REV

X00 X01 X02 A00

1

1

1

1

1 2

2

2

8 7 6 5

CE36 0.1U_0402_25V6

2

1 2 3 4

THERMATRIP3# CHARGER_SMBDAT CHARGER_SMBCLK

<46>

1 1 2

1

1 2

100K_0804_8P4R_5%

1 @ RE59

2 2200P_0402_50V7K

I_ADP

@CE39 100P_0402_50V8J

*

CE40

4700p 4700p 4700p 4700p

RE81 10K_0402_5%

RE79

240K 130K 33K 1K

+3.3V_ALW

RE79 130K_0402_5%

EC5048_TX <35> Pin8 5085_TXD for EC Debug pin9 5048_TXD for SBIOS debug

CLK_PCI_LPDEBUG

+RTC_CELL

QE4 MMBT3904WT1G_SC70-3~D

+3.3V_ALW

LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 LPC_LFRAME# PCH_PLTRST#_EC

8 7 6 5

10K_8P4R_5%

THERMATRIP2# THERMATRIP3# THSEL_STRAP

@ CE46 100P_0402_50V8J

MSCLK MSDATA HOST_DEBUG_TX

+3.3V_RUN

1 2 3 4

BC_DAT_ECE1117 POA_WAKE# VCI_IN2#

CE24, CE26, CE27 Place near UE2

VSET_5085

1 RE64

RPE5

+3.3V_ALW2

RE69 8.2K_0402_5%

8 7 6 5

C

@ CE37 100P_0402_50V8J

1 2 3 4

+3.3V_ALW 2 1K_0402_5%

RE57

RE59 close to UE2 at least 250mils

@ CE35 100P_0402_50V8J

1

B13 A13 B14 A14 A15 B16 A16 B17 B15 A17 A12 B34 A2 B29 A46 B61 A57

ACAV_IN <46,47> ALWON <41>

RUNPWROK QE2B DMN66D0LDW-7_SOT363-6

QE2A DMN66D0LDW-7_SOT363-6

2

RUN_ON

@ RE75 100K_0402_5%

RE74 10K_0402_5%

RE73 10K_0402_5%

RE72 10K_0402_5%

2

+PECI_VREF PECI_EC_R

8 7 6 5

2.2K_0804_8P4R_5%

1

B51 A48

1 2 3 4

CHARGER_SMBDAT <46> CHARGER_SMBCLK <46> SIO_SLP_SUS# <9> PBAT_PRES# <40,46,47> USH_SMBDAT <27> USH_SMBCLK <27>

5085 Channel Location

+3.3V_ALW

EMI depop location

2

2

1 2

1

+3.3V_RUN RPE3

DOCK_SMB_DAT DOCK_SMB_CLK GPU_SMBDAT GPU_SMBCLK

A59

POWER_SW_IN# DOCK_PWR_SW# VCI_IN2# POA_WAKE#

<37,41>

+3.3V_ALW

DOCK_SMB_DAT <34> DOCK_SMB_CLK <34> A_ON <38> SIO_EXT_WAKE# <9,12> SYS_PWROK <9> ENVDD_PCH <10,23>

GPU_SMBDAT GPU_SMBCLK CHARGER_SMBDAT CHARGER_SMBCLK

B62 A64 A60 B67 A63 B63 B68

RE283 @

Thermal diode mapping

RE68 100K_0402_5%

2

2

DOCK_SMB_DAT DOCK_SMB_CLK A_ON

<36,38>

ALW_PWRGD_3V_5V

REM_DIODE2_P

JTAG_TDI JTAG_TMS JTAG_CLK JTAG_TDO

1 2 3 4 5 6 7 8 9 10

AC_PRESENT <9,12> SIO_PWRBTN# <9>

RUN_ON

2

+3.3V_RUN

+3.3V_ALW

RPE7 10K_8P4R_5%

RE71 49.9_0402_1%

11 12

1 2 3 4 5 G1 6 G2 7 8 9 10

SIO_PWRBTN#

RE67 10K_0402_5%

YE1 32.768KHZ_12.5PF_Q13FC135000040

2

2 1

MEC_XTAL2 CE29 27P_0402_50V8J

CE28 27P_0402_50V8J

@ RE65 100_0402_1%

CE30 1U_0402_6.3V6K

JTAG1 CONN@ @SHORT PADS~D

1

2

<36,38>

HB_A531015-SCHR21

CONN@ JLPDE1

PM_APWROK <9> RESET_OUT# <9,15> PCH_PCIE_WAKE# <9,35>

2 RE279 @

ALW_PWRGD_3V_5V_EC 1 0_0402_5%

@ DE1 RB751S40T1G_SOD523-2

1

@EMC@ CE34 4.7P_0402_50V8C

@EMC@ RE66 10_0402_5%

32 KHz Clock

+3.3V_ALW

A

RESET_OUT#

2 RE280 @

RUN_ON_EC 1 0_0402_5%

<30,42>

MEC5085-LZY_DQFN132_11X11

RUN_ON#

11 12

RUN_ON_EC

SIO_SLP_A# <9> EC_32KHZ_MEC5085 <30,35> ME_SUS_PWR_ACK <9>

SUS_ON

RE281@

SIO_SLP_S3# 1 0_0402_5%

CLK_PCI_MEC

Place close pin A29

1 2 3 4 5 6 7 8 9 10

ALW_PWRGD_3V_5V_EC

DP1/DN1

MEC_XTAL1

1 2 3 4 5 G1 6 G2 7 8 9 10

<37>

BREATH_LED# <34,39> BAT1_LED# <39> BAT2_LED# <39>

ESR <2ohms

JTAG_RST#

CONN@ JDEG1

PCH_RSMRST#

1

CE32 10U_0603_6.3V6M

RE63 100K_0402_5%

1

+3.3V_ALW

MSDATA MSCLK PCH_RSMRST# FWP#

CE31 4.7U_0603_6.3V6K

1

15mil

B

1 VREF_PECI PECI_DAT DN1_DP1A/THERM DP1_DN1A/VREF_T DN2_DP2A DP2_DN2A DN3_DP3A DP3_DN3A DN4_DP4A DP4_DN4A VIN VSET V THERMTRIP2# GPIO002/THERMTRIP3# GPIO024/THSEL_STRAP PROCHOT_IN#/PROCHOT_IO# V_ISYS0 V_ISYS1

PCH_ALW_ON

1 RE282 @

SUS_ON_EC 2 0_0402_5%

1

A61 A62

BGP0 VCI_OVRD_IN VCI_OUT VCI_IN0# VCI_IN1# VCI_IN2# VCI_IN3#

GPIO011/nSMI GPIO061/LPD# SER_IRQ LRESET# PCI_CLK LFRAME# LAD0 LAD1 LAD2 LAD3 CLKRUN# GPIO100/NEC_SCI

AGND

MEC_XTAL1 MEC_XTAL2_R 0_0402_5%

A6 A27 A28 B30 A29 B31 A30 B32 A31 B33 A32 A33

SYSPWR_PRES

SIO_SLP_S4# 2 0_0402_5%

ME_FWP_EC <6> RUNPWROK <9,35> EN_INVPWR <23> SIO_SLP_S4# <9> SIO_SLP_LAN# <9,28> USB_PWR_SHR_EN# <32,35> PCH_ALW_ON <38> SIO_SLP_S3# <9> PCH_DPWROK <9>

2

PCH_PLTRST#_EC CLK_PCI_MEC LPC_LFRAME# LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3

GPIO123/BCM_A_CLK GPIO122/BCM_A_DAT GPIO121/BCM_A_INT# GPIO032/BCM_E_CLK GPIO031/GPTP-OUT2/BCM_E_DAT GPIO030/GPTP-IN2/BCM_E_INT#/GANG_DATA7 GPIO047/LSBCM_D_CLK GPIO046/LSBCM_D_DAT/GANG_STROBE GPIO045/LSBCM_D_INT#

A3 B4 A4 B5 B7 A7 B48 B49 A47 B50 B52 A49 B53 A50

mCARD_PCIE#_SATA <6,12> LAN_WAKE# <12,28>

RUNPWROK EN_INVPWR

CE25 0.1U_0402_25V6

<12> SIO_EXT_SMI# <12> SIO_RCIN# <12,35> IRQ_SERIRQ <9,27,30,35> PCH_PLTRST#_EC <7> CLK_PCI_MEC <7,35> LPC_LFRAME# <7,35> LPC_LAD0 <7,35> LPC_LAD1 <7,35> LPC_LAD2 <7,35> LPC_LAD3 <9,12,35> CLKRUN# <12> SIO_EXT_SCI#

GPIO003/I2C1A_DATA GPIO004/I2C1A_CLK GPIO005/I2C1B_DATA/BCM_B_DAT GPIO006/I2C1B_CLK/BCM_B_CLK GPIO012/I2C1H_DATA/I2C2D_DATA GPIO013/I2C1H_CLK/I2C2D_CLK/GANG_DATA3 GPIO130/I2C2A_DATA/BCM_C_DAT GPIO131/I2C2A_CLK/BCM_C_CLK GPIO132/I2C1G_DATA GPIO140/I2C1G_CLK GPIO141/I2C1F_DATA/I2C2B_DATA GPIO142/I2C1F_CLK/I2C2B_CLK GPIO143/I2C1E_DATA GPIO144/I2C1E_CLK

HOST_DEBUG_TX

RE58 100K_0402_5%

A43 B45 A42 B20 A18 B19 A20 B21 A19

<35> BC_CLK_ECE5048 <35> BC_DAT_ECE5048 <35> BC_INT#_ECE5048 <46,47> ACAV_IN_NB <9> SIO_SLP_S5# <21> BEEP <37> BC_CLK_ECE1117 <37> BC_DAT_ECE1117 <37> BC_INT#_ECE1117

GPIO050/FAN_TACH1/GTACH0/GANG_START GPIO051/FAN_TACH2/GANG _MODE GPIO052/FAN_TACH3/GTACH1/GANG_ERROR GPIO053/PWM0 GPIO054/PWM1/GPWM1 GPIO055/PWM2 GPIO056/PWM3/GPWM0

A54 B58

<40,47>

1

B22 A21 B23 B24 A23 B25 A24

B57 B1 A55 A1 B28 B2 A8 B9 A9 B39 A44

AC_DIS

2

FAN1_TACH DOCK_POR_RST# SUS_ON_EC

FAN1_PWM

1

<34>

1

<40> PS_ID <9> SUSACK# BIA_PWM_EC

MEC_XTAL2 2 @ RE61

DOCK_PWR_BTN#

2

for no-dock : A43 use BC_CLK_ECE1099 for no-dock : B45 use BC_DAT_ECE1099 for no-dock : A42 use BC_INT#_ECE1099

2

1 2

DOCK_POR_RST#

<23>

C

10K_0402_5%

1

trace width 20 mils trace width 20 mils

100K_0804_8P4R_5%

2

2

<34>

1 RE42

BOARD_ID

1

for no-dock : A21 use LID_CL_SIO#

A10 B10 B8 B27 B44 B46 B26 A25 B36 B37 B38 A34 A35 A36 A40 B43 A45 B65

2

RUN_ON SUS_ON A_ON PCH_ALW_ON

<9,39>

2

1 2 3 4

GPIO151/GPTP-IN4/GANG_DATA2 GPIO152/GPTP-OUT4

3

RPE10

GPIO145/I2C1K_DATA/JTAG_TDI GPIO146/I2C1K_CLK/JTAG_TDO GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS JTAG_RST#

4

RE277

H_VSS

2

RE86

VSS_RO

A51 B55 B56 A53 B47

B18

JTAG_TDI JTAG_TDO JTAG_CLK JTAG_TMS JTAG_RST#

VR_CAP

1

MSDATA 10K_0402_5% DOCK_POR_RST# 100K_0402_5%

GPIO156/LED1/GANG_DATA1 GPIO157/LED0 GPIO153/LED2/GANG_DATA4 GPIO027/GPTP-OUT1 GPIO026/GPTP-IN1 GPIO001/ECSPI_CS1/32KHZ_OUT GPIO015/GPTP-OUT7 GPIO016/GPTP-IN8 GPIO017/GPTP-OUT8 GPIO107/NRESET_OUT GPIO125/GPTP-IN5/PECI_REQUEST#/GANG_BUSY

B54

2

GPIO007/I2C1D_DATA/PS2_CLK0B/I2C3A_DATA GPIO010/I2C1D_CLK/PS2_DAT0B/I2C3A_CLK/GANG_DATA0 GPIO110/PS2_CLK2/GPTP-IN6 GPIO111/PS2_DAT2/GPTP-OUT6 GPIO112/PS2_CLK1A GPIO113/PS2_DAT1A GPIO114/PS2_CLK0A GPIO115/PS2_DAT0A GPIO154/I2C1C_DATA/PS2_CLK1B/GANG_DATA5 GPIO155/I2C1C_CLK/PS2_DAT1B/GANG_DATA6

VSS_ADC

4.7K_8P4R_5% 1

VTR VTR VTR VTR VTR VTR

+VR_CAP B12

CLK_KBD DAT_KBD CLK_MSE DAT_MSE PBAT_SMBDAT PBAT_SMBCLK

A5 B6 A37 B40 A38 B41 A39 B42 B59 A56

VTR_ADC

VSS

SML1_SMBDATA SML1_SMBCLK <37> CLK_TP_SIO <37> DAT_TP_SIO for no-dock : A38 use LCD_TST <34> CLK_KBD for no-dock : B41 use Free <34> DAT_KBD for no-dock : A39 use SLP_ME_CSW_DEV# <34> CLK_MSE for no-dock :B42 use Free <34> DAT_MSE <40> PBAT_SMBDAT <40> PBAT_SMBCLK

CLK_KBD DAT_KBD CLK_MSE DAT_MSE

8 7 6 5

H_VTR

B60

1 2 3 4

GPIO021/RC_ID1 GPIO020/RC_ID2 GPIO014/GPTP-IN7/RC_ID3 GPIO025/UART_CLK GPIO120/UART_TX/V2P_COUT_HI1 GPIO124/GPTP-OUT5/UART_RX/V2P_COUT_LO1 VCC_PWRGD GPIO060/KBRST/BCM_B_INT# GPIO101/ECGP_SCLK GPIO103/ECGP_MISO GPIO105/ECGP_MOSI GPIO102/BCM_C_INT# GPIO104/SLP_S0# GPIO106 GPIO116/MSDATA/V2P_COUT_LO/TAP_SEL_STRAP GPIO117/MSCLK/V2P_COUT_HI GPIO127/A20M nFWP

B11

RPE2

VBAT

C1

1

1 2

2 1

1 1

1

1

1

1

1 2

2

2

2

2

2

1

CE19 0.1U_0402_25V6

CE23 0.1U_0402_25V6

CE18 0.1U_0402_25V6

B3 A11 A26 B35 A41 A52

<7> <7>

+5V_RUN

8 7 6 5

CE22 0.1U_0402_25V6

EN_INVPWR 100K_0402_5% RESET_OUT# 10K_0402_5%

CE17 0.1U_0402_25V6

2

RE56

A22 A58

PAD-OPEN1x1m

POWER_SW#_MB

D

2 @CE16 0.1U_0402_25V6

2

1

RE55

+3.3V_ALW_UE2

10K_0402_5%

@ CE44 1 2 1U_0402_6.3V6K

UE2 B64

PJP15 1 CE21 10U_0603_6.3V6M

1

+3.3V_ALW

2

2 FAN1_PWM 10K_0402_5% FAN1_TACH 10K_0402_5%

2

2

2

C

2

1

1 RE33

DOCK_PWR_SW#

CE45 1U_0402_6.3V6K

1 RE51

1U_0402_6.3V6K

CE12 1U_0402_6.3V6K

+3.3V_RUN

CE15 1U_0402_6.3V6K

CE20 0.1U_0402_25V6

D

POWER_SW_IN#

CE14 1U_0402_6.3V6K

CE13 0.1U_0402_25V6

+3.3V_ALW_UE2

RE48

1

1 2 +3.3V_ALW_UE2

@ CE10 1 2

E

RE43

+RTC_CELL +RTC_CELL

B

2

RE37

0_0402_5%

RE62 100K_0402_5%

1

BC_DAT_ECE5048 100K_0402_5% PBAT_SMBDAT 2.2K_0402_5% PBAT_SMBCLK 2.2K_0402_5%

RE31 100K_0402_5%

2

CE11 0.1U_0402_25V6

2

1

EP

1 @ RE32 1 RE36

+RTC_CELL_VBAT

2 1K_0402_5%

A

Channel 1 Thermal Monitoring Interface Strap Option HIGH Thermistor Readings LOW Diode Readings

REM_DIODE4_N

Rest=1.58K , Tp=96 degree

BOARD_ID rise time is measured from 5%~68%.

<7>

HB_A531015-SCHR21


4

3

2

Title

MEC5085 Size

Document Number

Date:


Rev 0.3

LA-A901P 1

Sheet

36

of

53

5

4

3

2

1

D

D

Touch Pad Keyboard

JKBTP1

1 2

+3.3V_TP

DAT_TP_SIO CLK_TP_SIO

+3.3V_TP +3.3V_ALW +5V_RUN

CONN@ E-T_6705K-Y16N-00L

1

BC_CLK_ECE1117

16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

2

1 2

1 2 2

<36>

@EMC@ CZ31 10P_0402_50V8J

C

@EMC@ CZ30 10P_0402_50V8J

1

CLK_TP_SIO

GND2 GND1

@ CZ29 0.1U_0402_25V6

CLK_TP_SIO

+5V_RUN +3.3V_ALW <36> BC_INT#_ECE1117 <36> BC_DAT_ECE1117

DAT_TP_SIO

16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

@ CZ28 0.1U_0402_25V6

<36>

KB_DET#

@ CZ27 0.1U_0402_25V6

DAT_TP_SIO

RZ19 4.7K_0402_5%

<36>

RZ18 4.7K_0402_5%

PAD-OPEN1x1m

<12>

1

18 17

2

2

+3.3V_TP

1

1

+3.3V_TP

PJP16

2

+3.3V_RUN

Place close to JKBTP1

C

EMI depop location

@ eDP Cable W CAM Part Number

RSMRST circuit

Description

@ LED FFC Part Number

DC02C007600

Description

H-CONN SET 13D MB-EDP-CAMERA NBX0001JG00

FFC 10P F P0.5 PAD0.3 172MM MB-LED/B 13D

@ eDP TS Cable W CAM

RESET#

3

Description

H-CONN SET 13D MB-EDP-CAMERA-TS NBX0001JK00

FFC 8P F P0.5 PAD.3 123MM MB-FP VALIDITY

@ eDP Cable W/O CAM 0.1U_0402_25V6

Part Number

Description

5 <36>

PCH_RSMRST#

1 2

RSMRST#

B

DC02C007D00 O

A

GND 3

2

VCC

@ FP FFC Part Number

DC02C007C00

@ CZ34 1 2

P

1

@ CZ35 0.01U_0402_16V7K

1

B

Description

+3.3V_ALW

4

PCH_RSMRST#_Q

G

2

2 1

@ RZ22 10K_0402_5%

@ UZ5 +5V_ALW_UZ5

2

Part Number

+3.3V_ALW

@ RZ21 33_0402_5%

1

+5V_ALW

<9>

DC02C007500

RT9818A-44GU3_SC70-3

Part Number

Description

NBX0001JI00

FFC 16P F P0.5 PAD=0.3 119MM MB-TP 13D B

@ SATA SPINDLE Cable Part Number

UZ6 TC7SH08FU_SSOP5~D

@ TP FFC

H-CONN SET 13D MB-EDP

Description

@ USH Board FFC Part Number

Description

NBX0001JJ00

FFC 26P G P0.5 PAD.3 88MM MB-USH/B 13D

H-CONN SET 13D MB-SPINDLE HDD

@ SATA Cable <36,41>

ALW_PWRGD_3V_5V

1 @ RZ51

Part Number

2 0_0402_5%

DC02C007400

Description H-CONN SET 13D MB-MSATA HDD

Part Number

Description

DC30100Q100

CONN SET 13F DCJACK-MB 2DW1003-041110F

Description BATT CR2032 3V 225MAH PA 5 W/C 30MM

@ FAN Part Number

Description

DC28A000800 FAN SET DAQ20 DC5V AB7405HB-HB3 ADDA

@ BATT Cable

DC02001X800

Part Number GC02001DS00

@ DC-IN Cable

Part Number

@ RTC BATT

Description H-CONN SET 13D MB-BATT CABLE

@ Speak Part Number

Description

PK230003Q0L SPK PACK ZJX 2.0W 4 OHM FG

A

A


4

3

2

Title

Keyboard Size

Document Number

Date:


Rev 0.3

LA-A901P Sheet 1

37

of

53

4

MPHYP_PWR_EN

1

<12>

1 3

2 0_0402_5%

3

EN_+V1.05SP

EN_+V1.05SP

<43>

D

1

+1.05V_M

2

ON

PJP18

VIN

VOUT

VIN

VOUT

+1.05V_RUN_UZ7

7

1

4 6 1

+1.05V_MODPHY

2

PJP36

2

PAD-OPEN1x3m

if MODPHY off keep DSC solution MODPHY timing spec 0.7V/us and <65us

+1.05V_RUN +1.05V_RUN Max Rating: 3284 mA

PAD-OPEN1x3m @

VBIAS CT

2

8 2

2

RUN_ON

RUN_ON

+5V_ALW

1

A_ON 1 @ RZ42

UZ7 <36>

@

+1.05V_RUN

2 0_0402_5%

CZ39 0.1U_0402_10V7K

4

5

@

2

1

3

@

RUN_ON 1 @ RZ41

@

CZ64 470P_0402_50V7K

QZ10A DMN66D0LDW-7_SOT363-6

6

1.05V_MODPHY_EN CZ25 220P_0402_50V7K

MPHYP_PWR_EN#

2

@


2

RZ16 100K_0402_5%

1

2

+3.3V_ALW2

D

+1.05V_RUN source

4

G

@

+1.05V_MODPHY

CZ38 10U_0603_6.3V6M

6 5 2 1

RZ5 100K_0402_5%

1

@ QZ6 SI3456DDV-T1-GE3_TSOP6

1

5 9

GND GND

1

+1.05V_M +5V_ALW

2

S

+1.05V_MODPHY

3

D

5

TPS22967DSGR_SON8_2X2

+10.5V_M Max Rating: 2495 mA For No-Vpro HW configs

TPS22965 EOL change to TPS22967

+1.05V_M

1

2

@ RZ44

+3.3V_ALW_PCH/+3.3V_M source

+1.05V_RUN 0.01_1206_1%

1

+3.3V_M

C

C

RZ47 0_0603_5%

2

+3.3V_ALW UZ8

<36>

3

A_ON

4

+5V_ALW <36>

5

PCH_ALW_ON

6 7

VIN1 VIN1 ON1 VBIAS

VOUT1 VOUT1 CT1

CT2

VIN2 VIN2

VOUT2 VOUT2

+3.3V_M_UZ8 1 @ CZ40

12

1 CZ41

2 470P_0402_50V7K

1 CZ42

2 470P_0402_50V7K PJP20 1 2

2 0.1U_0402_10V7K

11

GND

ON2

14 13

10 9 8

+3.3V_ALW_PCH_UZ8

+3.3V_ALW_PCH

15


CZ43 0.1U_0402_10V7K

GPAD

1

1 2

PAD-OPEN1x1m @

+3.3V_RUN

2

For No-Vpro HW configs +3.3V_M

1 @ RZ46

2 0_0603_5%

B

B

+5V_RUN

1

+3.3V_RUN/+5V_RUN source

PJP21 PAD-OPEN1x3m UZ9

3 4 RUN_ON

5 +3.3V_ALW

6 7

VIN1 VIN1

VOUT1 VOUT1

ON1

CT1

VBIAS

GND

ON2

CT2

VIN2 VIN2

VOUT2 VOUT2

+5V_RUN_UZ9 1 @ CZ44

12

1 CZ45

2 470P_0402_50V7K

1 CZ46

2 1000P_0402_50V7K PJP22 1 2 +3.3V_RUN

2 0.1U_0402_10V7K

11 10 9 8

+3.3V_RUN_UZ9

15


CZ47 0.1U_0402_10V7K

GPAD

14 13

1

1 2

2

+5V_ALW

PAD-OPEN1x3m

2

@

A

A


4

3

2

Title

Power control Size

Document Number

Date:


Rev 0.3

LA-A901P Sheet 1

38

of

53

5

4

3

HDD LED solution for White LED

2

1

Battery LED

<6>

2

QZ3B DMN66D0LDW-7_SOT363-6 4 3

SATA_ACT#

SATA_LED

3

RZ24 10K_0402_5%

1

+3.3V_ALW

QZ3A DMN66D0LDW-7_SOT363-6 1 6

DZ3

1

2

SATA_LED#

<36>

2

RB751S40T1G_SOD523-2

BATT_WHITE# BATT_YELLOW# D

MASK_SATA_LED# DZ4

<35>

2 390_0402_5%

1

<35>

1 RZ25

BAT2_LED#

QZ4 DDTA114EUA-7-F_SOT323-3

2

5

D

1

LED_SATA_DIAG_OUT#

2 SYS_LED_MASK#

1 RZ27

RB751S40T1G_SOD523-2

2 220_0402_5%

<36>

BAT1_LED#

1 RZ28

2 330_0402_5%

1 RZ32

BREATH_WHITE_LED_SNIFF# 2 150_0402_5%

WLAN LED solution for White LED Breath LED

+3.3V_ALW

3

+5V_ALW

<34,36>

QZ7A DMN66D0LDW-7_SOT363-6 1 6

WLAN_LED_Q#

2

BREATH_LED#

C

LED3 LTW-193ZDS5_WHITE 1 2

Place LED3 close to SW3

QZ9 DDTA114EUA-7-F_SOT323-3

2

WIRELESS_LED#

QZ7B DMN66D0LDW-7_SOT363-6 4 3 BREATH_LED#_Q

5

2 <30,35>

RZ31 100K_0402_5%

1

WLAN_LED

C

1

MASK_BASE_LEDS#

SYS_LED_MASK#

1 RZ34

1 RZ33

BREATH_WHITE_LED# 2 220_0402_5%

2 390_0402_5%

+3.3V_ALW @ CZ48 1 2

1

SYS_LED_MASK#

2

LID_CL#

B

O A

4

LED board CONN

MASK_BASE_LEDS#

UZ10 TC7SH08FU_SSOP5~D

3

<35,39>

G

<28,35>

P

5

0.1U_0402_25V6

+5V_ALW BREATH_WHITE_LED# SATA_LED BATT_YELLOW# BATT_WHITE# WLAN_LED

B

POWER & INSTANT ON SWITCH <9,36>

LID_CL# +3.3V_ALW

11 12

2 SW3

POWER_SW#_MB

<35,39>

CONN@ JLED1

1 2 3 4 5 6 7 8 9 10

1

1 2 3 4 5 6 7 8 9 10

B

GND1 GND2 E-T_6705K-Y10N-00L

4

3

SKRBAAE010_4P

LED Circuit Control Table

Fiducial Mark @ FD1 1

SYS_LED_MASK#

LID_CL#

FIDUCIAL MARK~D

Mask All LEDs (Unobtrusive mode) Mask Base MB LEDs (Lid Closed) Do not Mask LEDs (Lid Opened)

@ FD2 1 A

FIDUCIAL MARK~D

0 1 1

X 0 1

A

@ FD3 1

@ H19 H_4P0

@ H20 H_2P5N

@ H22 H_2P8

@ H24 H_3P3

1

1

1

1

@ H17 @ H18 H_3P2 H_2P4

1

@ H15 H_3P2

1

1

1

1

1

1

1

1

@ H6 @ H7 @ H8 @ H9 @ H10 @ H11 @ H12 @ H13 H_2P8 H_2P8 H_2P8 H_2P8 H_3P8 H_3P8 H_3P8 H_3P8

1

1

1

1

FIDUCIAL MARK~D

1

@ H1 @ H2 @ H3 @ H4 H_2P8 H_2P4 H_2P8 H_4P0

@ FD4 1

1

FIDUCIAL MARK~D


5

4

3

2

Title

PAD, LED Size

Document Number

Date:


Rev 0.3

LA-A901P 1

Sheet

39

of

53

5

4

3

2

1

+COINCELL

1

COIN RTC Battery PR1 1K_0402_5% +Z4012 2

+3.3V_RTC_LDO

@ JRTC1 1 3 2 1 G 4 2 G

+COINCELL

Primary Battery Connector

2

1

PC1 1U_0603_10V4Z

2

+PBATT 2

PR2 PRP2

PBAT_SMBCLK_C PBAT_SMBDAT_C PBAT_PRES#_C

8 7 6 5

1 2 3 4

PBAT_SMBDAT PBAT_SMBCLK

100K_0402_5%

<36> <36>

PBAT_PRES#

100_0804_8P4R_5% PD4 1

DEREN_40-42251-01001RHF

<36,46,47>

PQ1 DMG2301U-7 1P SOT23-3 2

1

3

3

1 2 3 4 5 6 7 8 9 10 11 12

1

EMC@ PC3 2200P_0402_50V7K 2 1

BAS40CW SOT-323

1

EMC@ PL2 FBMJ4516HS720NT_2P 1 2

PBATT+_C 1 2 3 4 5 6 7 8 9 10 GND GND

PD3

+3.3V_ALW


1

EMC@ PD2 TVNST52302AB0_SOT523-3

3

2

3

2

EMC@ PD1 TVNST52302AB0_SOT523-3

@PBATT1

D

TYCO_2-1775293-2~D

+RTC_CELL

1

1

3

D

DOCK_SMB_ALERT#

<34,35>

2 2

SDMK0340L-7-F_SOD323-2~D

GND

<34,35,47>

1

SLICE_BAT_PRES#

2 1

PR6 0_0402_5%

PC4 2

C

C

1500P_0402_50V7K

PD5

+3.3V_ALW PR7 1 0_0402_5%

EMC@ PL3 BLM15AG102SN1D_2P 2 1

<34>

2

2.2K_0402_5%

PR9 33_0402_5% 1 2

S 2 G

NO

IN

6

GND

V+

5

GPIO_PSID_SELECT

<35>

+5V_ALW

NB_PSID_TS5A63157

PQ2 FDV301N-G_SOT23-3

3

NC

COM

4

PS_ID

<36>

TS5A63157DCKR_SC70-6~D

+5V_ALW

PR11 10K_0402_1%

3

PC20

PC20 @EMC@ 0.1U_0402_25V6

2

2

PQ3 MMST3904-7-F_SOT323~D

PR12 15K_0402_1%

1 1

PC22

B

1

C

E

2

1

2 B

1

1

1

PD5 @EMC@ AZC199-02SPR7G_SOT23-3

B

PC22

1

DOCK_PSID

PR8

100K_0402_1%

2

3

PR10

2

3

D

1 2

NB_PSID

PU1

2

EMC12U@

1

@

AZC199-02SPR7G_SOT23-3

@ PR13 2

PSID_DISABLE#

<35>

0.1U_0402_25V6 EMC12U@

10K_0402_5%

DC_IN+ Source 10U_0805_25V6K

+DC_IN

5

PJP1 1

1 2

PC10 10U_0805_25V6K

<47>

2

SOFT_START_GC

A

PR18 2

DCX124EK-7-F PNP/NPN_SC74-6~D

2

10K_0402_5%

PR15

1

4

1M_0402_5%

1 PR14

<36,47>

PQ6A 6

CVILU_CI0805M1HRC-NH

AC_DIS

5

PR17 1 1

4

1

1 PR16

+DCIN_JACK

2

-DCIN_JACK

4.7K_0805_5%

7 6 5 4 3 2 1

@

A

GND GND 5 4 3 2 1

PC22 @EMC@ 10U_0805_25V6K 2 1

@ PJPDC1

PC21 @EMC@ 10U_0805_25V6K 2 1

EMC@ PC9 1000P_0603_50V7K 2 1

PQ6B 2

1 2 3 PC5 0.022U_0805_50V7K 1 2

3


+DC_IN_SS

PQ4 FDMC6679AZ_MLP8-5

100K_0402_5%

EMC15U@

DCX124EK-7-F PNP/NPN_SC74-6~D

EMC12U@

2

10U_0805_25V6K

1M_0402_5%

2


PAD-OPEN 1x3m

Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

4

3

2

+DCIN Size

Document Number

Date:


Rev 0.3

LA-A901P Sheet 1

40

of

53

A

PC105

B

PC106

PC105

2200P_0402_50V7K 0.1U_0402_25V6 EMC12U@

EMC12U@

PC105

PC106

C

2200P_0402_50V7K 0.1U_0402_25V6 EMC15U@

EMC15U@

1

+3.3V_ALW2 +3.3V_RTC_LDO

2200P_0402_50V7K 0.1U_0402_25V6

EMC14U@

PR100 6.49K_0402_1% 1 2

PR101 15K_0402_1% 1 2

4.7_1206_5% 680P_0603_50V7K EMC14U@

EMC14U@

PR111

PC111

1 FB_5V

16

UG_5V

VBST2

17

BST_5V

18

SW1

DRVL1

SW1

EN

5

15

EN1 20

VREG5

VIN

13

12

SW2

11

8

PC110 0.1U_0603_25V7K BST_5V_C 1 2 3 2 1

VBST1 SW2

4 PR109 2.2_0603_5% 1 2

LG_3V

LG_5V

4

4 PR112

+3V5V_PWR_SRC

3 2 1

PC114

4.7_1206_5% 680P_0603_50V7K EMC14U@

EMC14U@

PR112

PC114

2

PL102 3.3UH_6.3A_20% 1 2

4.7_1206_5% 680P_0603_50V7K EMC15U@

1

PR113 0_0402_5% 2

+5V_ALWP

4.7_1206_5% 680P_0603_50V7K

EMC15U@

2

+5V_ALW

PJP102 1

2

+3.3V_ALW

PAD-OPEN 1x3m

PC119 1U_0603_10V6K 2 1

2

5VALWP TDC 3.5 A Peak Current 5.0 A O Current 6.0 A TYP MAX H/S Rds(on) 24mohm , 30mohm L/S Rds(on) 13.5mohm , 16.5mohm Choke DCR 25mohm CAP ESR 18mohm

PAD-OPEN 1x3m

3VALWP TDC 4.5 A Peak Current 6.4 A O Current 7.68 A TYP MAX H/S Rds(on) 24mohm , 30mohm L/S Rds(on) 13.5mohm , 16.5mohm Choke DCR 15.5mohm CAP ESR 18mohm

+

PJP101 1

EMC15U@

+3.3V_ALWP

1

3

+5V_ALW2

EN

+5V_ALWP PC115 220U_6.3V_M

TPS51285BRUKR_QFN20_3X3 DRVH2 DRVH1

5

CS1

1 9

1

BST_3V

2

10

2

@EMC@ PR112 4.7_1206_5%

PC109 PR110 0.1U_0603_25V7K 2.2_0603_5% BST_3V_C 1 1 2 2

ALWON

PC102 10U_0805_25V6K

2 1

2

PR114 200_0402_1% 1 2

SNUB_5V

UG_3V

4

14 19

PGOOD

SIS412DN-T1-GE3_POWERPAK8-5 PQ101

7

21

SI7716ADN-T1-GE3_POWERPAK8-5 PQ103

PGOOD_3V_5V

VCLK

<36> EMC15U@

VFB1

VREG3

VFB2

1

PQ100 SIS412DN-T1-GE3_POWERPAK8-5 1 2 3 5

VO1

1

PC111

PAD

2

PR111

EN2

@EMC@ PC114 680P_0603_50V7K

3

PR106

PC118 4.7U_0603_10V6K 2 1

2

6

EN

PC117 0.1U_0603_25V7K 2 1

+

PQ102 SI7716ADN-T1-GE3_POWERPAK8-5 1 2 3 5

PC113 220U_6.3V_M

1

@EMC@ PC111 @EMC@ PR111 680P_0603_50V7K 4.7_1206_5% SNUB_3V 2 1 2 1

PL101 2.2UH_7.8A_20% 1 2

+3.3V_ALWP

PR108 0_0402_5% 1 2

CS2

PR107 100K_0402_1%

@EMC@ PC106 0.1U_0402_25V6 2 1

PC101 10U_0805_25V6K 2 1

+PWR_SRC

@EMC@ PC105 2200P_0402_50V7K 2 1

2

PU100

2

2 PAD-OPEN 1x3m

4

PJP100 1

+3V5V_PWR_SRC

16.9K_0402_1%

FB_3V

3

+3.3V_ALW

5

+3V5V_PWR_SRC

PR104 10K_0402_1% 1 2

PC100 4.7U_0603_10V6K 2 1

2

ALW_PWRGD_3V_5V

DRVL2

2

PR103 0_0402_5%

PR105 20K_0402_1% 2 1

<36,37> @EMC@PL100 1UH +-20% 6.6A 1

1

PR102 10K_0402_1% 1 2

4

E

PC106

1

EMC14U@

D

@

4

DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date: A

B

C

D

+5V_ALW/3.3V_ALW Document Number

Rev 0.3

LA-A901P Thursday, March 06, 2014

Sheet E

41

of

53

5

4

PC203

PC206

PC203

2200P_0402_50V7K 0.1U_0402_25V6 EMC15U@

+PWR_SRC

PC206

PC203

2200P_0402_50V7K 0.1U_0402_25V6

EMC15U@

3

EMC12U@

2

1

PC206

0.675Volt +/- 5% TDC 0.7 A Peak Current 1.0 A O Current 2.6 A fix by IC

2200P_0402_50V7K 0.1U_0402_25V6

EMC12U@

EMC14U@

EMC14U@

PJP200 1.35V_B+

PC208

4.7_1206_5% 680P_0603_50V7K EMC14U@

EMC14U@

PR203

PC208

14

1 2

VTT

VTTREF VDDQ

2

+V_DDR_REF

3 +V_DDR_REF

4

+1.35V_MEN_P

5

6

+5V_ALW

PC213 100P_0402_50V8J 1 2 PR206

1

2

768K_0402_1%

S5_1.35V

1

1

SUS_ON

PC212 0.033U_0402_16V7K

PR205 8.06K_0402_1% 1 2

1.35V_FB

1.35V_B+

C

FB sense trace when FB pull down to GND

2

7

PR204 0_0603_5%

PR207 0_0402_5% 1 2

PC205 22U_0805_6.3V6M

20

19

17

18 BOOT

21 1

FB

VDD

PC211 1U_0603_10V6K

GND

RT8207MZQW_WQFN20_3X3

VDDP

S3

11

CS

8

+5V_ALW

VTTSNS

S5

VDD_1.35V

2

PAD

VTTGND

PGND

TON

5

1 5.1_0603_5%

1 2 3

@EMC@ PR203 4.7_1206_5% SNUB_1.35V 2 1

12

4

PQ201 SI7716ADN-T1-GE3_POWERPAK8-5

PU200

CS_1.35V

PC209 1U_0603_10V6K

PR202

LGATE

9

PR201 19.6K_0402_1% 1 2

VLDOIN

15

UGATE

4

PHASE

16

DL_1.35V

PGOOD

1

PC204

+0.675V_P

13

<30,36>

+1.35V_MEN_P

2

SW _1.35V

@EMC@ PC208 680P_0603_50V7K 2 1

PR203

PC207 220U_D2_2VY_R17M

+

2

1

DH_1.35V

1 2 3

PL200 1UH_11A_20% 1 2

C

+VLDOIN_1.35V

10

+1.35V_MEN_P

2

5

1 2

@EMC@ PC206 0.1U_0402_25V6

1 2

@EMC@ PC203 2200P_0402_50V7K

1

PC201 10U_0805_25V6K

2

1

PC200 10U_0805_25V6K

2

@

BOOT_1.35V

PAD-OPEN1x1m

PQ200 SIS412DN-T1-GE3_POWERPAK8-5

1

D

PJP201 BOOT_1.35V_C 1 PR200 2 2.2_0603_5%

1

2

PAD-OPEN 1x2m~D

0.22U_0603_16V7K

1

D

<18>

0.675V_DDR_VTT_ON

10K_0402_1% PR209

PR210 0_0402_5% 1 2

@ PC214 .1U_0402_16V7K

2

EMC15U@

1

EMC15U@

2

4.7_1206_5% 680P_0603_50V7K @ PC215

2

B

B

.1U_0402_16V7K

+1.35V_MEN_P

Mode S5 S3 S0

A

+1.35V_MEM TDC 6.6 A Peak Current 9.5 A O Current 11.4 A TYP MAX H/S Rds(on) 24mohm , 30mohm L/S Rds(on) 13.5mohm , 16.5mohm Choke DCR 7.4mohm CAP ESR 17mohm

S3 L L H

S5 +1.35V_MEN +V_DDR_REF +0.675V_P L off off off H on on off H on on on

FB sense trace

PJP203

1

1

2

PJP202

2

+0.675V_P

JUMP_1x3m

1

+0.675V_DDR_VTT

2

PAD-OPEN1x1m

+1.35V_MEN_P

PJP204

1

1

2

2

+1.35V_MEM

A

JUMP_1x3m

DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

4

3

2

+1.35V_MEN/+0.675V_DDR_VTT Size

Document Number

Date:


Rev 0.3

LA-A901P Sheet 1

42

of

53

5

4

PC311

3

2

1

PC300

D

D

0.1U_0402_25V6 EMC14U@

2200P_0402_50V7K EMC14U@

PC311

PC300

EMC12U@

EN_+V1.05SP

2200P_0402_50V7K EMC12U@

EN_+V1.05SP

PC300

<38>

1M_0402_1% PR303

PJP300

+1.05V_MP

2

PC311

1

0.1U_0402_25V6

1

1

2

+1.05V_M

2

JUMP_43X118

0.1U_0402_25V6 EMC15U@

@EMC@ PR305 @EMC@ PC301 4.7_1206_5% 680P_0603_50V7K 1 2SNB_1.05V 1 2

PJP302

SY8208DQNC_QFN10_3X3

2

1

1

+3.3V_ALW

2

PR310 10K_0402_1% 2 1

1

PR315 100K_0402_1%

2

@ PR308 0_0402_5%

+1.05V_MEM TDC 5.7 A Peak Current 8.1 A O Current 9.72 A TYP MAX Choke DCR 13.0mohm , 14.0mohm

B

PR305

1 2

1 2

1 2

+3.3V_ALW

C

@ PC308 22U_0805_6.3VAM

5

1

LDO

2

PG

PC307 22U_0805_6.3VAM

1.05V_MP_PWROK 2

PC306 47U_0805_6.3V6M

2

1

1

1.05V_M_PWRGD

FB_+V1.05SP

4 7

+1.05V_MP

2 PC305 47U_0805_6.3V6M

BYP

PL301 0.68UH +-20% 7.9A 1

1

ILMT

FB 3

SW_+V1.05SP

10

2

LX

PC302 PR312 0.1U_0603_25V7K 0_0603_5% BST_+V1.05SP 1 2 BST_+V1.05SP_C 1 2

PC304 330P_0402_50V7K

GND

1 6

PR309 1K_0402_5% 2 1

9

PR313 0_0402_5%

2

EN BS

ILMT_1.05V

@ PR306 0_0402_5% ILMT_1.05V

IN

PR307 7.5K_0402_1% 2 1

10U_0805_25V6K PC303 2 1

8

PC310 4.7U_0603_6.3V6K

+V1.05SP_B+

PC309 4.7U_0603_6.3V6K 2 1

<9>

2

1 2

C

1

PU300

2

@EMC@ PC300 2200P_0402_50V7K

1

PAD-OPEN 1x2m~D

+3.3V_ALW

EMC15U@

@EMC@ PC311 0.1U_0402_25V6

+PWR_SRC

2200P_0402_50V7K

PC301

4.7_1206_5% 680P_0603_50V7K EMC14U@

EMC14U@

PR305

PC301

B

4.7_1206_5% 680P_0603_50V7K EMC15U@

EMC15U@

A

A

DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 5

4

3

2

+1.05V_M Size

Document Number

Date:


Rev 0.3

LA-A901P Sheet 1

43

of

53

5

4

3

2

1

+3.3V_RUN D

D

1

+5V_ALW PJP400

2

PC400 1U_0402_6.3V6K

1 PC401 4.7U_0805_6.3V6K

3

2

1 2

PU400

PC403 0.01U_0402_25V7K

1

PR402 8.66K_0402_1%

APL5930KAI-TRG_SO8

+1.5V_RUN

PAD-OPEN1x1m

1

2 9

PJP401

1

1.5VSP

2

VIN

+1.5V_VIN

2

FB

5 4

1

1 2

1

PC404 22U_0805_6.3V6M

PR403 10K_0402_1%

C

2

2

@ PR401 47K_0402_5%

EN

GND

8

1

2

100K_0402_5%

C

VIN VOUT VOUT

@EMC@ PC402 .1U_0402_16V7K

1

PR400

POK

2

7

+3.3V_RUN

VCNTL

6

2

1

PAD-OPEN1x1m

+1.5V_RUN TDC 0.47 A Peak Current 0.67 A

B

B

A

A

DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

+1.5V_RUN Size

4

3

2

Rev 0.3

LA-A901P Date:

5


Sheet 1

44

of

53

5

4

3

2

1

PL501

PC520

PC521

VREF

PR509

1

PR539 0_0402_5% 1

@ PR513 1 2 75_0402_1%

2

PWM1

2

PC503

EMC12U@

+VCC_CORE

1

CSD97374CQ4M_SON8_3P5X4P5

1 PC509 1U_0603_10V7K

PR501

+5V_RUN

4.42K_0402_1% EMC12U@

301K_0402_1%

2

PR512 2.15K_0402_1% 2 1

PR521

CSP1

3.92K_0402_1% EMC14U@

PR514 20K_0402_1% 2 1

PR521

1 2

PR529 110_0402_1%

1 2

PR528 75_0402_1%

1 2

2

1

PR501 PR527 54.9_0402_1%

3

PC511 0.1U_0402_25V6

301K_0402_1% EMC15U@

3.92K_0402_1% EMC15U@

VIDALERT_N

<15>

VIDSOUT

B

CSN1

VIDSCLK

<15>

2

EMC12U@

2SKIP#

PR520 0_0402_5%

PR521

C

PL500 0.15UH_PCME064T-R15MS0R667_36A_20% 4 1

CORE_SW

4 3 2 1SKIP#1

1

PR501

EMC12U@

1

2

PGND2 PWM BOOT VSW PGND1 BOOT_R VDD VIN SKIP#

VCORE Load line & IMON

VIDALERT_N

PR534 0_0402_5%

TI recommend 1nF

EMC14U@

<15>

PC508

4.7_1206_5% 680P_0603_50V7K PU501

9 8 1 2 CORE_BOOT 7 0.1U_0402_25V6 2 1 CORE_BOOT_R 6 5 PR517 2.2_0603_5% PC504

B

@

EMC14U@

PR522

PR515 3.01K_0402_1% 2 1 2

+1.05V_VCCST

1000P_0402_50V7K 1 2

PC505 1U_0603_10V6K

1

H_PROCHOT#

VIDSCLK

1

PC514

<9,36,46>

EMC14U@

1

+3.3V_RUN

316K_0402_1%

1

1

PR526 10_0603_1%

2

+5V_ALW

PC510 1U_0603_10V7K

1

2

2

<15>

PC513 0.068U_0402_16V7K

1

1_0603_5%

4.7_1206_5% 680P_0603_50V7K H_VR_READY

1 2 PC502 0.068U_0402_16V7K

PR519

47P_0402_50V8J

PC507 1 2 0.33U_0603_10V7K PC512 1500P_0402_50V7K 2 1

1 PR535 4.75K_0402_1%

PC508

PH501 10K_0402_1%_TSM0A103F34D1RZ

2 TPS51624RSM_QFN32_4X4

VR_HOT#

2

VREF

EMC15U@

PR522

+3.3V_RUN

1.91K_0402_1%

4.87K_0402_1%

1 PR523 2 10K_0402_5%

EMC15U@

@EMC@ PC508 680P_0603_50V7K

@ PR516

2

@EMC@ PR522 4.7_1206_5% CORE_SNUB 2 1

1

@ PR521 1 2

100P_0402_50V8J

4.7_1206_5% 680P_0603_50V7K

2

8 7 6 5 4 3 2 1

DROP COMP VREF V5A GND VR_HOT# VCLK ALERT# GND 25 26 27 28 29 30 31 32 33 @ PC506 1 2

PC508

PWM1

VR_ON SKIP# PWM1 PWM2 N/C PGOOD VDD VDIO

C

2

PR522

2

CSP1 CSN1 CSN2 CSP2 PU3 N/C GFB VFB

VFB

<15>

+

SKIP#

VIDSOUT

17 18 19 20 21 22 23 24

H_VR_EN

1

@EMC@ PC521 0.1U_0402_25V6 2 1

PR536 1 0_0402_5%

VBAT SLEWA THERM IMON O-I B-RAMP F-IMAX O-USR

CSN1

GFB

@EMC@ PL501 1 2 FBMA-L11-453215800LMA90T_2P

16 15 14 13 12 11 10 9

PU500

+3.3V_RUN +3.3V_RUN

+VCC_PWR_SRC PC519 100U_D_20VM_R55M

2 CSP1

2

PAD-OPEN 4x4m

2

D

EMC15U@

PJP500

1

@ PC518 10U_0805_25V6K 2 1

PR511

PC521

EMC15U@

@ PC517 10U_0805_25V6K 2 1

1

10K_0402_5%

EMC12U@

PC520

680P_0402_50V7K 0.1U_0402_25V6

EMC15U@

+PWR_SRC

PC516 10U_0805_25V6K 2 1

2

FBMA-L11-453215800LMA90T_2P 20K_0402_1%

PR508

1

100K_0402_1%

2

O-USR

CORE_BOOT_C

+VCC_PWR_SRC

EMC12U@

PL501

@EMC@ PC520 2200P_0402_50V7K 2 1

2 1 PR504

36.5K_0402_1%

2 PR503

1

681K_0402_1%

2 PR502

1 2

PR507

1

1 PR506

F-IMAX 150K_0402_1%

B-RAMP

2

O-I

75_0402_1%

2 PR501

1

365K_0402_1%

@

2200P_0402_50V7K 0.1U_0402_25V6

EMC12U@

1

PR510 39K_0402_5%~N

@

39K_0402_1%

PC500 1 2

2

2

SLEWA

PC501 .1U_0402_16V7K 2 1

PR505 10K_0402_5% 1 2

1 D

4700P_0603_50V7K

PH500

2 @ PR500 75_0402_1%

FBMA-L11-453215800LMA90T_2P

IMON

PC515 10U_0805_25V6K 2 1

1

100K_0402_1%_N15WF104F03RC

<15>

VCCSENSE

from processor VSSSENSE

2

VFB

PR532 0_0402_5% 1

2

GFB

U 15W TDC 10 A Peak Current 32 A O Current 38.4 A DC Load line -2.0 mV/A Icc_Dyn_VID1 27 A Choke DCR: 0.66m +-7% ohm PH500 B Value : 4250k 1% PH501 B Value : 3370k 1%

1

+VCC_PWR_SRC

<17>

PR531 0_0402_5% 1

2

@ PR518 2M_0402_1% A

A

1

2

O-I

@ PR524 2M_0402_1%

1


@ PR525 27K_0402_1%


2

Title

5

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4

3

2

+VCC_CORE Size

Document Number

Date:


Rev 0.3

LA-A901P Sheet 1

45

of

53

B

C

D

EMC@ PL700 1UH +-20% 6.6A 2

2

PAD-OPEN 4x4m

PQ701 NTR4502PT1G_SOT23-3 PQ703A SI3993CDV-T1-GE3_TSOP6

S

6

D

5

2

PR728 0_0402_5% 1 2

+PWR_SRC

PC708 22U_0805_25V6M 2 1

PC707 22U_0805_25V6M 2 1

PC705 10U_0805_25V6K 2 1

3

@

@

PC717 22U_0805_25V6M 2 1

PC716 22U_0805_25V6M 2 1

PC715 22U_0805_25V6M 2 1

PC714 22U_0805_25V6M 2 1

@EMC@ PC713 2200P_0402_50V7K 2 1

@EMC@ PC732 0.1U_0402_25V6 2 1

2

ISYS /PROCHOT

GND

CMPIN

NC

/BATPRES

SRN

CELL

/BATDRV

PWPD

BAT

21

1

CHARGER_CELL_PIN

PJP701 2

PQ705 AON6970_DFN5X6D-8-7 PL701 2.2UH_12A_20% 2

1

+VCHGR

PR721 0.01_1206_1% 4

1

3

2

20 19 PR722 4.02K_0402_1% 1 2

18 17

1

2

PR723 10_0603_1% 2

PC729 1U_0603_25V6K GNDA_CHG

1

1

BQ24770_REGN

2

1

GNDA_CHG

+PWR_SRC

22

10K_0402_1%

CMPOUT

BQ24777RUYR_WQFN28_4x4

@ PR729 154K_0402_1%

@

PAD-OPEN1x1m

PC727 0.1U_0402_25V6 1 2

@

@ PC728 0.1U_0402_25V6 1 2

GNDA_CHG GNDA_CHG

2

GNDA_CHG

PC726 0.1U_0402_25V6 1 2

PC725 10U_0805_25V6K 2 1

16

PC706 22U_0805_25V6M 2 1

1 PR707 100K_0402_1% 2 1

PR706 100K_0402_1% 1 2

1

2 A

ACN

CHG_LGATE

/BATPRES

29

PBAT_PRES#

LODRV

SRP 15 <47>

H_PROCHOT#

PR725 100K_0402_1% <36,40,47>

13

CMPOUT 14

Near PL701

PC724 10U_0805_25V6K 2 1

<9,36,45>

CHG_SW

23

IADP

PC723 10U_0805_25V6K 2 1

GNDA_CHG

PHASE

CHG_UGATE

26 27

PR799 CMPIN

EMC12U@

@EMC@ PC722 0.1U_0603_25V7K 2 1

1 BQ24770_REGN

GNDA_CHG

ACOK

2

I_SYS

10

2200P_0402_50V7K

EMC12U@

@EMC@ PC721 1000P_0603_50V7K 2 1 CHG_SNUB 1

<36>

0_0402_5% 2

HIDRV

7

I_BATT

PR717 1

BTST SDA

IDCHG

0.1U_0402_25V6

<47>

24 PR712 2.2_0603_5% 25 CHG_BTS 1 2 CHG_BTS_C

S1/D2

<36>

9

0_0402_5% 2 0_0402_5% 2 0_0402_5% 2

REGN

ACDET

G2

PR716 1 PR718 1 PR720 1

DK_CSS_GC

6

I_ADP

PR788 20K_0402_1% 1 2

<36>

PC719 100P_0402_50V8J 1 2

2

PR715 154K_0402_1%

PC718 100P_0402_50V8J 1 2

2 ACAV_IN 1

<36,47>

8

PC713

@EMC@ PR726 4.7_1206_5%

7

CHARGER_SMBCLK @ PT2 PAD~D

EMC14U@

1U_0603_10V6K

CMSRC

SCL

2200P_0402_50V7K

EMC14U@

PC710 1 2

S2

5

GNDA_CHG BQ24770_REGN

1

2 0_0402_5%

2

<36>

PR709 0_0402_5% 2 1

2

1 PR714

2

D1

12

PR713 100K_0402_1%

1

S2

11

1

PC713

PC732

3

PC711 2

VCC

<34>

PC712 0.047U_0603_25V7K~D 2 1

6

ACDRV

28

+DCIN

4

GNDA_CHG PU700

3

0.1U_0402_25V6 GNDA_CHG @ PT1 PAD~D <36> CHARGER_SMBDAT

2

1

PC709 10U_0805_25V6K 2 1

PC702 0.1U_0402_25V6 1 2

DOCK_DCIN_IS-

PC732

0.1U_0402_25V6

4

PC703 0.1U_0402_25V6

2

PR710 294K_0402_1% 2

PC701 1U_0603_25V6K 1 2

1

BQ24770_REGN

PR711 49.9K_0402_1% 2 1

1

CHARGER_SMBCLK CHARGER_SMBDAT pull up 10K in HW side (R827 R828)

PR708 10_1206_5%

<34>

G

SDMK0340L-7-F_SOD323-2~D +SDC_IN

AC Det Max:16.82V Typ :16.54V Min :16.26V

2

D

1

DOCK_DCIN_IS+

PQ703B SI3993CDV-T1-GE3_TSOP6 S

2

PR703 100_0402_1% 2 1

CSSN_1

1

PD702

0_0402_5%

2


PR705 1

+DC_IN_SS

2

PD704

G

PR704 0_0402_5% CSSP_1 1


PC704 10U_0805_25V6K 2 1

3

1

S

S

2 G PQ702 NTR4502PT1G_SOT23-3

1

TYP MAX H/S Rds(on) 7.4mohm , 8.8mohm L/S Rds(on) 2.6mohm , 3.1mohm Choke DCR 5.8mohm , 7.0mohm

D 2 G D

PD705 +DOCK_PWR_BAR

3

G1

2

0_0402_5% 2

2

S2

PR702 1

CSS_GC

1

1

<47> <47>

3

DC_BLOCK_GC

2

2

1

1

1 1

CHAGER_SRC PJP700

4 @

4

PR700 1 0_0402_5%

1

+PWR_SRC_AC @

PC700 0.1U_0603_25V7K

+DC_IN_SS

PR701 0.01_1206_1%

+SDC_IN

4

PQ700 SI4835DDY-T1-GE3_SO8 8 1 7 2 6 3 5

5

A

+DC_IN

GNDA_CHG

BATDRV#

1

3

PR726

<47>

3

PC721

2

PR737 649K_0402_1%

PC737 100P_0402_50V8J

4.7_1206_5% 1000P_0603_50V7K

CMPOUT

2

PR738 3M_0402_5%

1

CMPIN 1

PR745 100K_0402_1% 2 1

EMC12U@

EMC12U@

PR726

PC721

2

1

2

ACAV_IN_NB

1

<36,47>

2

PR743

0_0402_5%

PC741 100P_0402_50V8J

4.7_1206_5% 680P_0603_50V7K

2

1

PR740 10K_0402_1%

EMC14U@

EMC14U@

PR726

PC721

+3.3V_ALW 4.7_1206_5% 1000P_0603_50V7K EMC15U@

EMC15U@

4

4

DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A

B

C

Charger Size

Document Number

Date:


Rev 0.3

LA-A901P D

Sheet

46

of

53

3

2

1

Purpose: Trigger PROCHOT# when active battery is removed from system. Allows EC to re-establish system performance for battery next in line.

+PBATT

+3.3V_ALW

2

5

2

8 7 6 5

3

2

PQ810 FDS6679AZ-G_SO8

1

PBAT_PRES#

B

<35>

PR812 0_0402_5% 1 2

DIS_BAT_PROCHOT#

4

O A

3

2

G

STSTART_DCBLOCK_GC

1 2 3 1

4

PD808 PDS5100H-13_POWERDI5-3

<36,40,46>

P

5

4 BATDRV#

6

PC805 0.1U_0402_10V7K 1 2

PU804

DMN65D8LDW-7_SOT363-6

PQ806A

4

+3.3V_ALW

PR811 0_0402_5% 1 2

PC807 1 2 0.47U_0805_25V6K

<46>

PQ806B

1 PR810 100K_0402_5%

PQ800 SI4835DDY-T1-GE3_SO8 1 8 2 7 3 6 5

1

+VCHGR

2

PD800 PDS5100H-13_POWERDI5-3 3 1 2

2

PR813 100K_0402_5%

+3.3V_ALW D

PR815 100K_0402_5%

1

+PWR_SRC_AC

1

+3.3V_ALW

3

4

@ PR816 0_0402_5% 1 2

/BATPRES

<46>


5

D

TC7SH08FU_SSOP5~D

PR814 330K_0402_5% 2 1

5

+DOCK_PWR_BAR PQ826 FDMC6679AZ_MLP8-5

1 2 3

PR822

PQ815

A

1 ACAV_IN#

2

+3.3V_ALW2

C

2

DOCK_DET#

<34,35,47>

3

PD813

1


1

2 G 3

S

+3.3V_ALW2

Vth=0.5-1.5V

2

PR864 100K_0402_5%

2

2

1

0_0402_5%

D

1

2

1

PR895

3

1

+3.3V_ALW

1

PQ829 DMG2301U-7 1P SOT23-3

PQ816 DMN65D8LW-7_SOT323-3

8 7 6 5

2

FDS6679AZ-G_SO8

B

O 3

1 10K_0402_5%

4 4

0.1U_0402_10V7K

P

5

TC7SH08FU_SSOP5~D

100K_0402_5%

DMN65D8LDW-7_SOT363-6 1 6

PU806

1

2

1500P_0402_50V7K

PR819 2

1

PC810 2 1

G

2 PR818

1

@ PC809

100K_0402_5%

+3.3V_ALW2

C

Purpose: Turn on the PQ817 for primary or module bay battery to provide power to dock side without AC exist.

PQ817A

1 2 3

4

2

PR830 100K_0402_5%

2

PR829

1

+DC_IN_SS

5

+DOCK_PWR_BAR

PR853 0_0402_5%

1

3

2 2

PR827 1 2 100K_0402_5%

2

PR832 0_0402_5% 1 2

PR831 0_0402_5% 1 2

+3.3V_ALW2

ACAV_IN

3

PQ817B <36,46,47> PD817 3

5

+DC_IN_SS

2

+NBDOCK_DC_IN_SS


S

3

1

PQ813B DMN65D8LDW-7_SOT363-6 4

3

100K_0402_5%

D PQ832 DMN65D8LW-7_SOT323-3

100K_0402_5%

B

1

2

2 G

PR826

4

2 1

PR828 1 2 10K_0402_5%

AC_DIS

3

<36,40>

6 2

PQ814 NTR4502PT1G_SOT23-3

ACAV_IN# PQ813A DMN65D8LDW-7_SOT363-6 1

1 B

+SDC_IN

PR847 0_0402_5% 1 2

ERC1 CD3301_SDC_IN

<46>

DC_BLOCK_GC PR851

<36,46,47>

ACAV_IN

1

1 2 3 4 5 6 7 8 ACAVIN P33ALW2 9

2

DC_IN SS_GC ERC1 ACAVDK_SRC GND SDC_IN DC_BLK_GC ACAV_IN P33ALW2

0_0402_5% 37

+3.3V_ALW2

1

2

TP

0_0402_5%

ERC2

ERC3

DOCK_AC_OFF

3

+5V_ALW

BAT54CW_SOT323-3

<34>

PR844 10K_0402_5%

2

PR845

P50ALW PBATT_OFF DK_AC_OFF_EN ACAV_IN_NB GND DK_AC_OFF_EN SL_BAT_PRES# BLKNG_MOSFET_GC NBDK_DCINSS

<46> CSS_GC <46> DK_CSS_GC

27 26 25 24 23 22 21 20 19

SLICE_BAT_ON

<35>

0_0402_5%

DK_AC_OFF 3301_ACAV_IN_NB DK_AC_OFF_EN SL_BAT_PRES#

PR848 0_0402_5% 1 2 1

PR850

PR854 0_0402_5% 1 2

CD3301BRHHR_QFN36_6X6~D PR859 0_0402_5% 1 2

<35>

2

1M_0402_5% SLICE_BAT_PRES#

<34,35,40>

+NBDOCK_DC_IN_SS 1

+3.3V_ALW

<36,46>

DOCK_AC_OFF_EC PR858 1

@ PR863 0_0402_5% 1 2

P33ALW

ACAV_IN_NB

2 0_0402_5%

PR857

2

EN_DOCK_PWR_BAR

<35>

0_0402_5% A

EN_DK_PWRBAR PC817 0.1U_0402_25V4Z~D 2 1

PC816 0.047U_0603_25V7M 2 1

PC815 0.1U_0603_25V7K 2 1

A

PR843 0_0402_5% 1 2

CD_PBATT_OFF1

10 11 12 13 14 15 16 17 18

PR855

36 35 34 33 32 31 30 29 28

PU800 PR842 0_0402_5% 1 2ACAVDK_SRC

ACAV_DOCK_SRC#

1

+PBATT P50ALW

NC CHARGERVR_DCIN DC_IN_SS DK_PWRBAR GND NC BLK_MOSFET_GC DSCHRG_MOSFET_GC PBatt+

PR846 <40> SOFT_START_GC 1 2 100K_0402_5%

<34>

DOCK_DET#

2

CSS_GC DK_CSS_GC ERC3 ERC2 GND PWR_SRC SS_DCBLK_GC EN_DK_PWRBAR P33ALW

+3.3V_ALW2

<34,35,47>

PD815 PR838 0_0402_5% 1 2

2

PC813 0.1U_0603_50V4Z

1

CD3301_DCIN

2

2

PR835

1

47_0805_5%~D 1

+DC_IN

DC_IN_SS DK_PWRBAR

1

BAT54CW_SOT323-3

@

STSTART_DCBLOCK_GC PR860 0_0402_5% 1 2

3301_PWRSRC

PR874 1 2 1M_0402_5%

+PWR_SRC_AC


5

4

3

2

Title

Selector Size

Document Number

Date:


Rev 0.3

LA-A901P 1

Sheet

47

of

53

5

4

3

2

1

+VCC_CORE

D

D

1

2

1 PC900 22U_0805_6.3V6M

1

2

+

2 C

1 PC913 22U_0805_6.3V6M

2

2

1 PC902 22U_0805_6.3V6M

1 PC914 22U_0805_6.3V6M

2

2

1 PC903 22U_0805_6.3V6M

1 PC915 2.2U_0805_10V6K

2

2

PC904 22U_0805_6.3V6M

1 PC916 2.2U_0805_10V6K

2

@ PC917 22U_0805_6.3V6M

PC966 220U 2.5V Y D2 ESR9M H1.9 SX

1

2

1 PC901 22U_0805_6.3V6M

C

B

B

A

A

DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5

4

3

2

PROCESSOR DECOUPLING Size

Document Number

Date:


Rev 0.3

LA-A901P Sheet 1

48

of

53

5

4

3

2

1

Version Change List ( P. I. R. List ) Item Page#

Title

Request Date Owner

Issue Description

Solution Description

D

D

1

47

Selector

10/8

Compal

Remove slice battery circuit

Remove PD821, PQ831, PR825, PU808

2

45

VCC_CORE

10/8

Compal

To prevent acoustic noise issue

Remove PC923, PC924, PC925, PC926, PC927, PC928, PC929, PC930, PC931, PC940, PC941, PC943, PC946, PC947, PC948 Add PC966

X01

3

42

1.35V_MEN

10/8

RICHTEK

To prevent IC damage

Add PR204

X01

4

46

Charger

10/8

Compal

Fine tune divider voltage

Change PR713, PR725 to 100k Change PR715, PR729 to 154k

X01

Change Change Change Change Change

X01

C

5

B

Rev.

41,43,44

+1.05V_M +1.5V_RUN +3V/+5V

10/22

Compal

To improve the ability of anti-noise

PC808, PQ801, PR802, PR834,

PC811, PQ807, PR804, PR836,

PC812 , PC814, PD806, PD807, PD811, PD814, PD819, PQ809, PQ811, PQ812, PQ818, PQ821, PQ828, PQ830, PR808, PR813, PR815, PR816, PR817, PR821, PR823, PR837, PR839, PR849, PR852, PR861, PU805, PU807,

X01

PR307 to 7.5k PR310, PR102, PR104, PR403 to 10k PR100 to 6.49k PR101 to 15k PR402 to 8.66k

C

6

46

Charger

10/25

Compal

Change /BATPRES pin control net from /BATPRES to PBAT_PRES#

Pop PR728 Depop PR816

X01

7

45

VCC_CORE

10/31

Compal

Fine tune IMON

Add PR518, PR524, PR525

X01

8

ALL

ALL

10/31

Compal

RF request

Add PC521, PC206, PC106, PC311, PC732 ( 0.1uF )

X01

9

ALL

ALL

10/31

Compal

RF request

Pop PR111,PC111,PR112,PC114,PR203,PC208,PR305,PC301,PR522,PC508, (4.7ohm, 680pF)

X01

10

46

Charger

10/31

Compal

To prevent V trigger PROCHOT#

PR703 change to 100ohm

X01

B

A

A

DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5

4

3

2

PWR P.I.R (1/1) Size

Document Number

Date:


Rev 0.3

LA-A901P Sheet 1

49

of

53

5

4

3

2

1

Version Change List ( P. I. R. List ) Item Page# D

Title

Date

Request Owner

Issue Description


Rev.

1

6

HW

2013/10/8

COMPAL

Follow intel reference circuit.

Add CC100, RC300 on U pin AC4, net name is PM_TEST_RST

0.2(X01)

2

27

HW

2013/10/8

COMPAL

Dell drop POA function.

Change JUSH1 from 26 pin to 20 pin, pin define follow E5

0.2(X01)

3

36

HW

2013/10/8

COMPAL

Dell drop POA function.

remove POA_WAKE# off page symbol remove POA_ON/OFF#,make UE2.B62 to be NC pin

0.2(X01)

4

22

HW

2013/10/9

COMPAL

IC version changed.

VMM2320 circuit change: 1. UV8 from VMM2320 change to VMM 2330 (SA00007G800) 2. UV8 pin J3, E5 to +1.05V_RUN 3. VMM_SPI_WP# reserved RV517, 2.2K resistor PU to +3.3V_RUN_VMM 4. VMM_GPIO4,reserved RV518, 2.2K resistor PU to +3.3V_RUN_VMM 5. VMM_GPIO5 reserved RV519, 2.2K resistor PU to +3.3V_RUN_VMM 6. add QV20,CZ69,RV210,RV212,QV21 external FET switch circuit 7. UV8 pin B5, B6 change to +3.3V_RUN_VMM 8. LP_CTL add RV516, 2.2K resistor PU to +3.3V_RUN_VMM 9. Depop RV73 10. add LP_EN on UV8.A5 (10/18) 11. depop QV20,CZ69,RV210,RV212, QV21 external FET switch circuit (10/24) 12.RPV2 pin1 & pin2 NC (11/4)

0.2(X01)

Change LI1,LI2,LI3,LI4,LI5,LI6,LI7,LI8,LI9,LV3,LV6,LV10,LV12,LV27 From SM070003K00 (S COM FI_ CHILISIN CMMI21T-900Y-N) To SM070003Y00 (S COM FI_ MURATA DLW21HN900HQ2L)

0.2(X01)

C

5

23

6

9

7 8

HW

2013/10/9

COMPAL

Follow EMC suggestion

HW

2013/10/9

COMPAL

reserved for S3 within 2s , system shutdown issue debug.

add RC26, , reserved RC27.

36

HW

2013/10/9

COMPAL

board ID change.

RE79 change to 130K

36

HW

2013/10/14

COMPAL

follow intel latest design guide.

pop RE56 and change from 8.2K to 10K , it's resistor

B

9 10

7 20,23,31,32

D

C

0.2(X01) 0.2(X01) RESET_OUT# pull down

0.2(X01) B

HW

2013/10/16

COMPAL

RF requirement.

add CC14, CC15 and move CC12, CC13 to behind the

resistor

(RC72)

HW

2013/10/17

COMPAL

follow ESD recommend list.

change all ESD diode N change DI2, DI3, DI5, DV4 from SCA00001100(S ZEN ROW PJDLC05C 3P C/A SOT23) to SC600001600(S DIO ROW AZC199-02S.R7G C/C SOT23 ESD) change DI1,DI6,DI4 from SC300002800(S DIO(BR) TVWDF1004AD0 DFN ESD) to SC300002C00(S DIO(BR) L05ESDL5V0NA-4 SLP2510P8 ESD) change DA1,DA2,DA3,DA6,DA7 from SCA00001L00(S ZEN ROW L30ESDL5V0C3-2 C/A SOT23 ESD) to SCA00002900(S ZEN ROW L03ESDL5V0CC3-2 C/A SOT-23 ESD)

0.2(X01) 0.2(X01)

A

A


4

3

2

EE P.I.R (1/4) Size

Document Number

Date:


Rev 0.3

LA-A901P Sheet 1

50

of

53

5

4

3

2

1


Title

Date

Request Owner

Issue Description


Rev.

11

7,38

HW

2013/10/17

COMPAL

for UMA DOCK configure, it has non-VPRO configure.

add PJP33, PJP34 UC3, CC7, RC50, RC55, RPC12, UZ7, CZ64 change to VPRO@ 0.2(X01)

12

38

HW

2013/10/17

COMPAL

power doesn't split VPRO & NPRO BOM.

add RZ41, RZ42, reserve it for VPRO & NVPRO option.

0.2(X01)

13

39

HW

2013/10/17

COMPAL

SSI design will cause LED behavior error.

remove QZ5, QZ7.2 & QZ3.2 change to SYS_LED_MASK#

0.2(X01)

14

20

HW

2013/10/17

COMPAL

To solve Line-on HDD dirty shut down issue.

add UN3, CN3, CN4, PJP7 and reserved it.

0.2(X01)

15

30,36

HW

2013/10/17

COMPAL

follow Dell requirement.

add back SUS_ON, change +3.3V_SUS control pin to SIO_SLP_S4# 1. UL3.3 from SIO_SLP_S4# to SUS_ON 2. UE2.B23 → SUS_ON_EC , RPE10.2 → SUS_ON 3. add RE282(Pop), RE281(depop) 4. add RE279, RE280 ( dock only) 5. UE2.B9 → RUN_ON_EC

0.2(X01)

C

D

C

16

23

HW

2013/10/18

COMPAL

follow ESD recommend.

LZ1 change from SM070001N00 to SM070003Y00

0.2(X01)

17

12

HW

2013/10/24

COMPAL

add GPIO pin for DIMM quantity detection.

add DIMM_DET on UC1.U4

0.2(X01)

18

6

HW

2013/10/24

COMPAL

debug usage.

add RC301

0.2(X01)

19

9

HW

2013/10/28

COMPAL

reserve it to prevent PCH_PLTRST# floating when power on

add RC304, 100K pull down, on PCH_PLTRST#_EC

0.2(X01)

20

30

HW

2013/10/29

COMPAL

New SIM connector has no this pin.

remove UIM_DET on JNGFF2 pin58

0.2(X01)

21

23

HW

2013/10/29

COMPAL

it's designed for Goliad, Houston doesn't need.

remove RZ1

0.2(X01)

B

to replace PCH_GPIO48, remove

B

22

30

HW

2013/10/29

COMPAL

To solve WWAN can not detec issue.

Add RZ43, 100k pull up for WWAN_PWR_EN

0.2(X01)

23

38

HW

2013/10/29

COMPAL

for VPRO & NVPRO BOM option.

remove PJP33, PJP34, PJP19 add RZ44, RZ46, RZ47

0.2(X01)

24

12

HW

2013/10/29

COMPAL

To solve backdrive issue.

Change TPM_PIRQ# pull up ( RC247) to +3.3V_RUN from +3.3V_ALW_PCH

0.2(X01)

25

37

2013/10/29

COMPAL

Dell request.

add RZ48, RZ49, QZ12 depop UZ5, UZ6, RZ21, RZ22, CZ35,RC91 (11/4) add RZ51, change QZ12 from 3904 to 3906. make RPE6 to be NC pin, add RE88 (11/4)

0.2(X01)

HW

A

A


4

3

2

EE P.I.R (2/4) Size

Document Number

Date:


Rev 0.3

LA-A901P Sheet 1

51

of

53

5

4

3

2

1


C

Title

Date

Request Owner

Issue Description


Rev.

26

30

HW

2013/10/30

COMPAL

Dell doesn't MODPHY.

add PJP36, depop QZ6, QZ10, RZ16, RZ5, CZ25, CZ38

0.2(X01)

27

28

HW

2013/11/04

COMPAL

SSI design will cause LED behavior error.

Change QL1, QL2 contorl pin from MASK_BASE_LEDS# to SYS_LED_MASK#

0.2(X01)

28

21

HW

2013/11/04

COMPAL

EMC request.

Add RA42, RA43.

0.2(X01)

29

21

HW

2013/11/05

COMPAL

follow vender suggestion. It's for 15KV ESD fail issue.

add CA12, CA13 change DA1, DA2, DA3, DA4 from GNDA to GND

0.2(X01)

30

12

HW

2013/11/05

COMPAL

GPIO 14 is sus power well, it has risk to cause back drive.

move TPM_PIRQ# from PCH_GPIO14 to PCH_GPIO17, add T21 on PCH_GPIO14

0.2(X01)

31

30

HW

2013/11/05

COMPAL

follow vender request.

RZ43 from 100K change to 0 ohm

0.2(X01)

32

20

HW

2013/11/06

COMPAL

For SATA repeater setting

RN11,RN16 pop 0ohm

0.2(X01)

33

28

HW

2013/11/06

COMPAL

For EMI request

RL21~ RL28 change to 2.2 ohm

0.2(X01)

41

20

HW

2013/11/06

COMPAL


RN11,RN16 pop 0ohm

0.2(X01)

42

30

HW

2013/11/05

COMPAL

follow vender request.

RZ43 from 100K change to 0 ohm

0.2(X01)

43

9,11,27, 35,36

HW

2013/11/20

COMPAL

follow vender suggest to solve "Bo" noise issue

1.UA1 pin22 add RA45 0 ohm PU to +3.3V_RUN_AUDIO 2.UA1 pin21 add RA44 100k ohm to GND

0.2(X01)

44

12,22

HW

2013/11/20

COMPAL

follow vender suggest

1.RPC8 change from 2.2k to 10k 2.UC1.F2 &RPC8.3 change name from 3.UC1.F3 &RPC8.4 change name from 4.UC1.G4 &RPC8.1 change name from 5.UC1.F1 &RPC8.2 change name from 6.RPV2.1 connect to I2C1_SDA_VMM 8.RPV2.2 connect to I2C1_SCL_VMM

0.2(X01)

I2C0_SDA to PCH_GPIO4 I2C0_SCL to PCH_GPIO5 I2C1_SDA_VMM to PCH_GPIO6 I2C1_SCL_VMM to PCH_GPIO7

B

D

C

B

45

22

HW

2013/11/27

COMPAL

To solve CRT display jitter issue

LV23,LV25 change from BLM15AX102SN1D to BLM15PX181SN1D

0.2(X01)

46

36,37

HW

2013/11/27

COMPAL

Base on Pre-PT RSMRST EA result

1.POP RE88,UZ6,RE51 2.remove QZ12,RZ48,RZ49,RZ50

0.2(X01)

47

6

HW

2013/11/29

COMPAL

follow intel DG, ESR MAX=50 ohm

Change YC1 from SJ100001K00(S CRYSTAL 32.768KHZ Q13FC1350000400) to SJ10000LD00(S CRYSTAL 32.768KHZ 12.5PF 9H03220008)

0.2(X01)

48

22

HW

2013/12/10

COMPAL

follow vender suggestion

1. change LV22,LV24 from SM01000N400(S SUPPRE_ MURATA BLM15AX102SN1D 0402) to SM01000NO00(S SUPPRE_MURATA BLM15PX181SN1D 0402) 2. change CV82, CV94 from 1uF to 10uF 3. UV8 pin D3 from +1.05V_VMM_VDDTX to+1.05V_VMM_VDD. 4. UV8 Pin H3, E10, H11 change to NC 5. Change UV8 pin B5, B6 from +3.3V_RUN_VMM to +3.3V_RUN_VDDIO

0.2(X01)

A

A


4

3

2

EE P.I.R (3/4) Size

Document Number

Date:


Rev 0.3

LA-A901P Sheet 1

52

of

53

5

4

3

2

1

Version Change List ( P. I. R. List ) Item Page#

Title

Date

Request Owner

Issue Description


Rev.

D

D

49

34

HW

2013/12/18

COMPAL

To solve Power leakage issue.

Change R272 from 10K to 100K, and pull up to +3.3V_ALW2

0.2(X01)

50

21

HW

2013/11/05

COMPAL

follow ESD/vender request

1. change RA42, RA43 to LA10, LA1 SM01000NA00(S SUPPRE_ MURATA BLM15PX330SN1D 0402) 2. change RA7, RA8 from 16 to 24.9 ohm 3. DA1 &DA3 change from SCA00002900 to SCA00001B00(S ZEN ROW AZ5123-02S.R7G 3P C/A SOT23) 4.CA4&CA1 change from 220pF(@EMC@) to 680pF(EMC@)

0.2(X01)

51

26

HW

2013/12/18

COMPAL

Base on CRT EA result

change CV51, CV52, CV53 from 12pF to 2.2pF

0.2(X01)

52

20

HW

2013/12/18

COMPAL


De-pop RN9,RN13

0.2(X01)

HW

2014/02/06

COMPAL

For MODPHY power rail contril by JUMP directly

1.change PJP36 pin1 from +1.05V_M to +1.05V_RUN 2.depop QZ6, QZ10, RZ16, RZ5, CZ25, CZ38

0.3(X01)

For PI0, delete RV66 For PI1, add RV100 PD to GND

0.3(X01)

53

38

C

C

54

25

HW

2014/02/06

COMPAL

Base on PS8338 datasheet, PI0 have 2 level, PI1 have 3 level

55

36

HW

2014/02/10

COMPAL

EC request, for Delray common code reserved. add RE283(@)

0.3(X01)

56

29

HW

2014/02/27

COMPAL

EMI test fail , back to SSI SD card connector.

change JSD1 from TAITW_PSDCT6-20GLBS1NN4H_19P-T to ALPS_SCDADA0101_19P_NR

0.3(X01)

57

9,16

HW

2014/03/03

COMPAL

follow intel DG 1.2

1.reserved 0.47uF for +PCH_VCCDSW3_3 , near U AH10 pin 2.add 10K pull high to +PCH_VCCDSW3_3 for PM_LANPHY_ENABLE, leave RPC19. pin 3 NC

0.3(X01)

58

30

HW

2014/03/05

COMPAL

intel Wigig need 32K clock when DSx

1.Add UZ11&RZ56(@)&RZ57 2.JNGFF1 change to WIGIG_32KHZ from SUSCLK 3.JNGFF2.60 change to NC from SUSCLK

0.3(X01)

B

59

27

HW

2014/03/05

COMPAL

B

1. reserved CZ68 47nF on pltrst_ush# to GND. 2. Pop R6,R41,R273 to 10 ohm 3. Pop C42,C43,C319 to 4.7pF

EMC team Solution

0.3(X01)

A

A


4

3

2

EE P.I.R (4/4) Size

Document Number

Date:


Rev 0.3

LA-A901P Sheet 1

53

of

53

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