Dma 8257 1hx3w

Direct memory access

Direct memory access Direct memory access (DMA) is a process in which an external device takes over the control of system bus from the U. DMA is for high-speed data transfer from/to mass storage peripherals, e.g. harddisk drive, magnetic tape, CD-ROM, and sometimes video controllers. For example, a hard disk may boasts a transfer rate of 5 M bytes per second, i.e. 1 byte transmission every 200 ns. To make such data transfer via the U is both undesirable and unnecessary. The basic idea of DMA is to transfer blocks of data directly between memory and peripherals. The data don’t go through the microprocessor but the data bus is occupied. “Normal” transfer of one data byte takes up to 29 clock cycles. The DMA transfer requires only 5 clock cycles. Nowadays, DMA can transfer data as fast as 60 M byte per second. The transfer rate is limited by the speed of memory and peripheral devices.

Basic process of DMA For 8088 in maximum mode: The RQ/GT1 and RQ/GT0 pins are used to issue DMA request and receive acknowledge signals. Sequence of events of a typical DMA process 1) Peripheral asserts one of the request pins, e.g. RQ/GT1 or RQ/GT0 (RQ/GT0 has higher priority) 2) 8088 completes its current bus cycle and enters into a HOLD state 3) 8088 grants the right of bus control by asserting a grant signal via the same pin as the request signal. 4) DMA operation starts 5) Upon completion of the DMA operation, the peripheral asserts the request/grant pin again to relinquish bus control. For 8088 in minimum mode: The HOLD and HLDA pins are used instead to receive and acknowledge the hold request respectively. Normally the U has full control of the system bus. In a DMA operation, the peripheral takes over bus control temporarily.

DMA controller

A DMA controller interfaces with several peripherals that may request DMA. The controller decides the priority of simultaneous DMA requests communicates with the peripheral and the U, and provides memory addresses for data transfer. DMA controller commonly used with 8088 is the 8237 programmable device. The 8237 is in fact a special-purpose microprocessor. Normally it appears as part of the system controller chip-sets. The 8237 is a 4-channel device. Each channel is dedicated to a specific peripheral device and capable of addressing 64 K bytes section of memory.

Memoria principala

U

HOLD HOLDA

Magistrala de adrese

MA

Magistrala de date

MD

Magistrala de comenzi

MC

HRQ HLDA

DRQ DACK

Controler DMA

PI/E Dispozitiv Periferic

Address buss A0-A15 8 BIT STB LATCH OE#

A0-A15 BUSEN HOLD HOLDA

AEN HRQ

A0-A3 A4-A7 CS/

HLDA

I8237A

ADSTB DB0-DB7 DREQ0-3

U

CLK RESETMEMR# MEMW# IOR# IOW#

CLOCK RESET MEMR# MEMW# IOR# IOW# D0-D7

Control buss Sistem data buss

DACK0-3

D0-D7 SelLBUS

9

BIOW#

12 13 14 15 16 17 18 19 B0

OE# B7

11 DIR

BIOR# SP#/EN#

I8286 A7 8 7

6

5

4

3

2

A0 1

LDAT0-7

PCLK CSDMA#

11

CS# CLK

12

30 DB0 29 28 27 26 23 22 21 DB7

MEMR# MEMW# IOR# IOW#

A0 I8237A

A7 DRQ0 DRQ1 DRQ2 DRQ3

HRQ 13 RESET 6

READY HLDA

7

I8286

11

10

DMARDY DMAHLDA

8 7 6 5

12 13 14 15

ADSTB

32 33 34 35 37 38 39 40 19 18 17 16

8 7 6 5 4 3 2 1

9

I8286

DIR OE#

12 13 14 15 16 17 18 19

DRQ0-3

25

DACK0 24 DACK1 14 DACK2 15 DACK3

DMAEN CK 3 D0 Q0 4 7 8 74LS 13 373 14 17 18 D7 OE# Q7 8 7 6 5

ADR0 ADR1 BIOW# CSPAGE#

2 5 6 9 12 15 16 19

Q0 12 D0 13 74LS 14 170 D3 Q3 15

3 WA 2 WB 1 WE#

MEMR# MEMW# IOR# IOW#

DIR OE#

36 EOP# 9 AEN

RESET

3 4 1 2

RA 17 RB 18 RE# 19

ADR8-ADR15

ADR16-ADR19

ADR0-ADR7

MASTER#

CLK CS1# XA0

XA1-XA7

XD0-XD7

12

11 32 33 34 35 37 38 39 40

A0

30 29 28 27 26 23 22 21

DB0

CS#

CLK EOP# AEN ADSTB

A7

AEN1#

36 9 8

74LS573

I8237A

DRQ0 DRQ1 DRQ2 DRQ3

DB7

3 4 1 2

MEMR# DACK0 MEMW# DACK1 IOR# DACK2 IOW# DACK3 6 READY 13 RESET HRQ HLDA 10

OE# C XA8-XA15

19 18 17 16

DRQ0-3

25 24 14 15

DACK0-3

T/C

7

CLK CS2# 32 33

XA8

A0

A7

CS#

CLK EOP# AEN ADSTB

I8237A

OE# C 74LS573

XA9-XA16

DB0

DB7

DRQ0 DRQ1 DRQ2 DRQ3

MEMR# DACK0 MEMW# DACK1 IOR# DACK2 IOW# DACK3 READY RESET HRQ HLDA HRQ HLDA

DRQ5-7

DACK5-7